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Browse Prior Art Database

RAS Buffering Technique to Prevent Stored Data Destruction in DRAM Standby State

IP.com Disclosure Number: IPCOM000103691D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 156K

Publishing Venue

IBM

Related People

Kazusawa, M: AUTHOR [+2]

Abstract

Disclosed is a Row Address Strobe (RAS) signal buffering technique in order to prevent data destruction for data stored in Dynamic Random Access Memory (DRAM) when RAS is activated incorrectly.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

RAS Buffering Technique to Prevent Stored Data Destruction in DRAM Standby State

       Disclosed is a Row Address Strobe (RAS) signal buffering
technique in order to prevent data destruction for data stored in
Dynamic Random Access Memory (DRAM) when RAS is activated
incorrectly.

      When DRAMs operate in a system card, there is a possibility
that signals of DRAM are disturbed by crosstalk of the card's signal
metal line, ground and power line's noise and a skew of DRAM control
devices, etc.  It usually appears as a glitch on signal lines.  When
glitch is made on signals of DRAM in the above mentioned ways, the
most critical case is on RAS signal in DRAM standby state because RAS
indicates DRAM activation and triggers signal sensing of memory cell.

      The wordline and bitline behavior in RAS error operation is
shown in Fig. 1.  The wordline is selected by high to low transition
of RAS, and the data which corresponds to the selected wordline
appears as one or two hundred millivolts voltage difference between a
pair of bitlines.  Then the data have to be amplified to around 3 or
5 volts voltage difference and written back to corresponding cells as
a refresh operation.  It takes a long time and it is specified as
tRAS in DRAM user's guide and specification.  It is quite important
because it determines DRAM data retention time.  If it is not
performed enough, DRAM would not be able to retain the stored data
because of short retention time.  When any glitch activates RAS
signals, minimum tRAS is not guaranteed and the stored data are not
amplified enough.  It causes DRAM data destruction in validation of
the system card.  This symptom also occurs in DRAM active state, but
glitches in DRAM active state are easy to find out in a system card
validation because the error address is specified exactly.  Logic
designers usually pay attention to DRAM active state; therefore, it
is quite rare to perform an incorrect operation for DRAM activation.
But glitches in DRAM standby state are much more difficult to find
out.  Because the addresses are not cared about in DRAM standby
state, there is no need to take care of address bus in DRAM standby
state for DRAM controller.  Other control signals, for example,
Column Address Strobe (CAS) or Write Enable (WE), are gated by
RAS-related signals in standby state. Any glitch which is made on
these signals in DRAM standby state is not critical.  In DRAM active
state, these signals cause an error operation.  But it is also rare
because the logic designer usually pays much attention to DRAM
activation.  It is easy to find out, too.  Hence, the glitch which is
made on RAS signal is the most critical and has to be removed.

      Conventional DRAMs take input buffer with hysteresis for noise
immunity.  Figs. 2 and 3 show the conventional RAS buffer and its
input-output...