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Threshold Controlled CMOS Chips for Low Power Low Voltage Applications

IP.com Disclosure Number: IPCOM000103693D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new method for controlling for threshold voltage of CMOS chips, which makes a CMOS technology optimized for high-performance usable for low-power applications without technology change. It detects the power supply voltage. If the power supply voltage is lower than a set value, the n-well and substrate generators are enabled, increasing the magnitude of the threshold voltage of the P and NMOS devices. Consequently, the chip leakage current decreases and the chip operates in a low-power mode.

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Threshold Controlled CMOS Chips for Low Power Low Voltage Applications

       Disclosed is a new method for controlling for threshold
voltage of CMOS chips, which makes a CMOS technology optimized for
high-performance  usable for low-power applications without
technology change.  It detects the power supply voltage.  If the
power supply voltage is lower than a set value, the n-well and
substrate generators are enabled, increasing the magnitude of the
threshold voltage of the P and NMOS devices.  Consequently, the chip
leakage current decreases and the chip operates in a low-power mode.

      Rapid progresses in portable electronics have increased the
importance of low-power CMOS chips, especially when the portable
equipment is operating under battery power.  For such applications,
reducing the leakage current of CMOS chips is very important.  On the
other hand, low-power electronics are very cost-sensitive because
most of the applications are related to low-end applications.  It
makes a great economic sense if a technology developed for
high-performance CMOS chips could be used for low-power applications
without any modifications.  Generally, the high-performance CMOS
technology has a lower threshold voltage and higher sub-threshold
conduction, resulting in a larger leakage current.  This makes the
technology unattractive for low-power applications.

      The new method described provides means for controlling the
leakage current without technology changes.  The new method detects
the power supply voltage.  Generally the power supply voltage for
low-power applications is lower than for the normal operations.  Once
the power supply voltage becomes lower than the set voltage, the
n-well and substrate generators bias the n-well and substrate above
VDD and below the ground potential (GND), respectively.  The
magnitude of the threshold voltage and sub-threshold conductance of P
and NMOS devices are dec...