Browse Prior Art Database

NFET Relay Sense Circuit

IP.com Disclosure Number: IPCOM000103697D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Iadanza, JA: AUTHOR [+3]

Abstract

Distributed sensing of a two-port memory cell structure by N-channel Field-Effect Transistor (NFET) local sense elements and Complementary Metal Oxide Silicon (CMOS) global sense elements, results in a single-ended data driven cascade read bitline sensing approach which is data driven. This approach provides relaxed timing requirements, improved circuit response time, improved sense signal stability, reduced power consumption, and reduced layout area compared with traditional differential sensing schemes.

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NFET Relay Sense Circuit

       Distributed sensing of a two-port memory cell structure
by N-channel Field-Effect Transistor (NFET) local sense elements and
Complementary Metal Oxide Silicon (CMOS) global sense elements,
results in a single-ended data driven cascade read bitline sensing
approach which is data driven.  This approach provides relaxed timing
requirements, improved circuit response time, improved sense signal
stability, reduced power consumption, and reduced layout area
compared with traditional differential sensing schemes.

      Fig. 1 shows the layout of the NFET Local Sense Element (LSE).
The LSE output is sent to a Global Read Bit Line (GRBL).  Local Read
Bit Line (LRBL) is precharged to ground through device S1, and GRBL
is precharged to Vdd prior to sensing.  When a read 0 (low) signal
comes in on  LRBL, device S2 remains off, and GRBL remains at Vdd.  A
read 1 (high level) on LRBL causes device S2 to turn on, discharging
GRBL to ground.

      Fig. 2 shows the layout of CMOS Global Sense Element (GSE).
Signals from LSE arrive at GSE through GRBL.  Precharge of GRBL to
Vdd is achieved by generating a low level on Read Bit Select Line
(RBSEL), which turns on device S3, precharging GRBL to Vdd.  Device
S7 remains off during this cycle, and Main Data Bus (MDB), which has
also been precharged to Vdd, remains in a high state.  At the
beginning of a read cycle, RBSEL is brought to a high level, turning
device S3 off, and device S7 on.  I...