Browse Prior Art Database

Master Slave Organization of DRAM Cache

IP.com Disclosure Number: IPCOM000103704D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 111K

Publishing Venue

IBM

Related People

Hwang, W: AUTHOR [+2]

Abstract

Disclosed is a master/slave organization technique of DRAM cache. By using this technique, both of the periodic refreshing and the reliability problems can be resolved even with the standard one transistor (1T) DRAM design. Also, a non-refreshing DRAM cache can be realized while improving the cycles per instruction (CPI) by 14 percent.

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Master Slave Organization of DRAM Cache

       Disclosed is a master/slave organization technique of
DRAM cache.  By using this technique, both of the periodic refreshing
and the reliability problems can be resolved even with the standard
one transistor (1T) DRAM design.  Also, a non-refreshing DRAM cache
can be realized while improving the cycles per instruction (CPI) by
14 percent.

      Assume that the DRAM cache can be divided into four portions,
as shown in the figure.  Region A is the master portion of the cache
and region B is the slave portion.  Both of the portions keep the
same image of blocks.  Regions C and D are other slave portions, but
their contents are two extra different blocks.  According to this
partition, this cache is changed from 4-way set associativity into
3-way associativity due to the fact that region B is the slave image
of A.  In the DRAM cache design, regions B, C and D are designed to
be refreshed periodically. However, region A is not refreshed at all.
According to the MRU observations [*], region A is the MRU region.
By the simulation results [*], region A will occupy above 85 percent
hits of the total hits.  The non-refreshed region A is based on the
basic DRAM characteristics - to read a DRAM is equivalent to write a
DRAM cell.  So read a DRAM block, this block is not necessary to be
refreshed in a certain period of time.  If this block is keeping
read, refreshment is not required until it is not read for a long
time.  But according to the temporary locality, this block may not be
needed in the future.

      The operation algorithm can be described as following:
1.  An extra bit is needed for region A.  This bit is used to
indicate the refreshment status.  It is cleared when the refresh
command is issued.  However, it is set when the block is read.  From
the figure, it is shown that region A and region B are the
direct-mapped cache.  But regions C and D are two-way cache.
2.  When all instructions are issued, the index field in this
instruction is used to find the block as show...