Browse Prior Art Database

Programmable Parallel Device Identification Mechanism for Personal Computers

IP.com Disclosure Number: IPCOM000103707D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 95K

Publishing Venue

IBM

Related People

Booth, JR: AUTHOR [+3]

Abstract

Described is a hardware implementation that provides a programmable parallel device identification mechanism for personal computers (PCs) so that advanced parallel port functions can be enabled for appropriate system/device configurations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Programmable Parallel Device Identification Mechanism for Personal Computers

       Described is a hardware implementation that provides a
programmable parallel device identification mechanism for personal
computers (PCs) so that advanced parallel port functions can be
enabled for appropriate system/device configurations.

      In prior art, data parity capability was added to the standard
parallel port connector to provide higher reliability.  However, this
function could only be enabled when both the system and a remote
device, such as a printer, would support this capability.  The
concept described herein provides a means to identify, through
program support, all combinations of parity devices, systems and
cables involved.  The objective is to have software control the
parallel device identification and configuration mechanisms so as to
enable parallel port data parity functions to be phased in
incrementally.

      The identification mechanism provides support for all
combinations of standard and advanced devices, system and cables.
Data parity capability can be introduced independently for each of
the components without compromising functionality of the whole
subsystem.  The user can gradually establish data parity capabilities
as required.

      Fig. 1 shows a block diagram of the system/device/cable
mechanism interaction that supplies the parity support.  The
mechanism can be invoked once during power-on system-test (POST) time
or every time a...