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Concurrent Register Loading from Memory and Register Storing to I/O

IP.com Disclosure Number: IPCOM000103709D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Balser, DM: AUTHOR [+2]

Abstract

The processor used in the IBM RISC System/6000* Model 220 has separate buses for memory and I/O, which gives it the flexibility to maintain a fully coherent cache system. This also has the impact of requiring the processor to be involved in all I/O transfers, both DMA and PIO. Communication with a graphics adapter is done through the I/O bus to minimize the interference with memory bus traffic. For high graphics performance, it is desirable to load or store multiple registers with a single instruction. The load string and store string instructions of the POWER Architecture* are ideal for this purpose. Optimally, we would like to execute a load string from memory while a store string to graphics is in process. The problems with this are: 1.

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This is the abbreviated version, containing approximately 52% of the total text.

Concurrent Register Loading from Memory and Register Storing to I/O

       The processor used in the IBM RISC System/6000* Model 220
has separate buses for memory and I/O, which gives it the flexibility
to maintain a fully coherent cache system.  This also has the impact
of requiring the processor to be involved in all I/O transfers, both
DMA and PIO.  Communication with a graphics adapter is done through
the I/O bus to minimize the interference with memory bus traffic.
For high graphics performance, it is desirable to load or store
multiple registers with a single instruction.  The load string and
store string instructions of the POWER Architecture* are ideal for
this purpose.  Optimally, we would like to execute a load string from
memory while a store string to graphics is in process.  The problems
with this are:
  1.  Insuring the store will not read a register before it is loaded
with the correct contents from memory.
  2.  Insuring a register is not loaded before its previous contents
can be read and stored to I/O.
  3.  A store string operation to I/O cannot be stopped once it has
started, because there is not a busy/wait concept for register
dependencies implemented in the coprocessor.

      These problems require that all registers utilized by a store
string instruction to I/O must be available before the coprocessor
microcode routine is started.

      The advantage of overlapping the loading and storing of data
registers is that the rate of transfer for graphics data becomes
limited by the coprocessor microcode length or the graphics adapter,
not by the fixed point unit.  This can have the effect of nearly
doubling the transfer rate otherwise attainable.

      By dividing the 32 architected fixed point data registers into
two groups of 16, it is possible to detect dependencies by perform...