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CSEF Circuit with Reduced Internal Logic Swing

IP.com Disclosure Number: IPCOM000103712D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Dennison, RT: AUTHOR

Abstract

The speed of a Current Switch Emitter Follower (CSEF) circuit can be improved by reducing the signal voltage swing. A clamping scheme is proposed which allows reduction of the voltage swing on the internal CSEF circuits.

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CSEF Circuit with Reduced Internal Logic Swing

       The speed of a Current Switch Emitter Follower (CSEF)
circuit can be improved by reducing the signal voltage swing.  A
clamping scheme is proposed which allows reduction of the voltage
swing on the internal CSEF circuits.

      The input signal of the CSEF circuit shown in Fig. 1 is
referenced to VR.  However, the signal which drives the input (the
emitter follower (EF) output) is derived from the VCC supply.  Thus,
the signal swing of the CSEF circuit must be large enough to maintain
adequate noise margins with both VCC and VR variations.  If the input
signal and the reference voltage of the CSEF are derived from the
same supply, then the signal swing can be reduced substantially.

      Fig. 2 shows a CSEF circuit with the disclosed clamping scheme
which allows reduction of the voltage swing on the current switch
collector nodes.

      The clamp, which controls the CSEF up-level, consists of
resistors R1 and R2, transistors T1 and T2 and Schottky diode S1.
The node labeled VC is clamped at a voltage given by:
      VC = VR + VBE(T1) - VF(S1) + VBE(T2).
The up-level at the EF output is given by:
      V1 = VC - RCL*IB(TEF) - VBE(TEF).
The down-level at the EF output is determined by ICS, RCL and SCL.
If ICS is large enough to turn on SCL, then the down-level is given
by:
      VO = VC - VF(SCL) - VBE(TEF).
The levels can be optimized by appropriate adjustments of the various
circuit components.  An approximation of the levels can be obtained
with the following assumptions:
      IB(TEF) = 0.0
      VBE(T1) = VBE(T2) = VBE(TEF) = VBE
      VF(S1) = VF(SCL) = VF.
Thus, the levels are given by:
      VC = VR + 2*VBE - VF
      V1 = VR + VBE - VF
      VO = VR + VBE - 2*VF.
The logic swing is approximately:
      V1 - VO = VF.
Note that both the up and down levels are independent of the VCC, VT
and VE supplies (to a first-order approximation).  Also note that the
switching threshold of the driven circuit is VR and that the critical
voltages at the driven circuit are:
      V1 - VR = VBE - VF
      VO - VR = VBE - 2*VF.

      The noise margin at the driven circuit depends on VBE, VF and
the VR mistracking between the clamp and the driven circuit.  The
on-chip mistracking can be reduced to about 10 mv with careful design
of the power busing.  With the standard CSEF, VR and VCC power supply
variations are several times larger than the VR mistracking and,
thus, the signal levels must be larger to maintain sufficient noi...