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Submicron Gate Ge/GaAs Double Heterojunction JFETs with Improved Electrical Performance

IP.com Disclosure Number: IPCOM000103713D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 161K

Publishing Venue

IBM

Related People

Mohammad, SN: AUTHOR [+2]

Abstract

The structural design and performance advantages of a Ge/GaAs double heterojunction JFET (shown schematically in Fig. 1) has been described. In the proposed JFET a thin (about 70 o) p--GaAs (5x1016cm-3) layer would first be grown epitaxially on a lowly doped (Nd=7x1016cm-3) n-type substrate. It would be followed by the growth of a non-uniformly doped n-type Ge layer (doping density Nd=2-5x1018 cm-3 near the gate side and Nd=2-5x1017cm-3 near the bottom) for active channel, and finally a p-GaAs layer (about 1016cm-3) for gate.

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Submicron Gate Ge/GaAs Double Heterojunction JFETs with Improved Electrical Performance

       The structural design and performance advantages of a
Ge/GaAs double heterojunction JFET (shown schematically in Fig. 1)
has been described.  In the proposed JFET a thin (about 70 o) p--GaAs
(5x1016cm-3) layer would first be grown epitaxially on a lowly doped
(Nd=7x1016cm-3) n-type substrate.  It would be followed by the growth
of a non-uniformly doped n-type Ge layer (doping density Nd=2-5x1018
cm-3 near the gate side and Nd=2-5x1017cm-3 near the bottom) for
active channel, and finally a p-GaAs layer (about 1016cm-3) for gate.

      The p--GaAs layer between n-Ge and n-GaAs would be a buried
layer, leading to the formation of p-n junction: one between n-GaAs
and p--GaAs, and the other between n-Ge and p--GaAs.  Due to low
doping level of p--GaAs buried layer, and of n-GaAs layer substrate,
the capacitances generated on both of the n+Ge/p--GaAs and
p--GaAs/n-GaAs junctions would be very low.  (Note that capacitance
of a junction depends on the doping of the less heavily doped side of
the junction).  Furthermore, the large area of p--GaAs layer adjacent
to n-Ge would be depleted of mobile carriers leaving stationary
negative charges (i.e., ionized acceptors).  This will result in a
precise carrier confinement in Ge, and, in turn, a well-defined
channel thickness, providing a uniform channel thickness improved
threshold voltage uniformity.

      If Vbi is the built-in voltage, and Vp is the pinch-off voltage
of a JFET, its threshold voltage VT would be given by [1] VT =
Vbi-Vp, where:

                            (Image Omitted)

e is the dielectric constant of Ge, a is the channel width, and y is
the spatial coordinate.

      It may be noted from the above formulas that the threshold
voltage becomes less negative when the channel width a and the
channel doping Nd are small.  The channel width can be made small by
judiciously confining it between two p--GaAs layers.  However, when
Nd is lowered to reduce the threshold voltage, there occurs an
increase in the channel resistance R.  So, as a compromise, the
doping should be made Gaussian with a high value near the gate side
of the channel and a low value near the substrate side of the
channel.  In this case, the electrons would tend to be close to the
gate side of the channel [2] while flowing from source to drain.  Use
of Gaussian would permit the reduction of effective channel width
without a reduction in channel resistance.  As the doping level is
lowered to about 1015 cm-3 near the n-Ge/p-GaAs junction underneath
the channel, the large negative threshold voltage could be brought
closer to zero.

      If a high voltage is applied at the drain of a short-channel
JFET (channel length L < 0.3 mm) the field in the depletion region
near the drain becomes high enough to generate electron-hole pairs.
Due to the influence of drain voltage VD, the...