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Browse Prior Art Database

MSIS Accessing Store Fetch Look Aside using Addresses

IP.com Disclosure Number: IPCOM000103723D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 147K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+4]

Abstract

MSIS (Multisequencing a Single Instruction Stream) is a uniprocessor organization in which a set of processing elements (PEs) working in concert execute Segments of the instruction stream. The Segments are either P-Segments, normal uniprocessor instruction stream portions, that are processed in the E-MODE of MSIS and produce Z-Segments, or the Z-Segments that are processed in Z-MODE by MSIS. The main difference between E-MODE and Z-MODE is that during E-MODE each PE sees all instructions in the Segment and executes the ones that are assigned to it, but during Z-MODE, a PE only sees the instructions assigned to it.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

MSIS Accessing Store Fetch Look Aside using Addresses

       MSIS (Multisequencing a Single Instruction Stream) is a
uniprocessor organization in which a set of processing elements (PEs)
working in concert execute Segments of the instruction stream.  The
Segments are either P-Segments, normal uniprocessor instruction
stream portions, that are processed in the E-MODE of MSIS and produce
Z-Segments, or the Z-Segments that are processed in Z-MODE by MSIS.
The main difference between E-MODE and Z-MODE is that during E-MODE
each PE sees all instructions in the Segment and executes the ones
that are assigned to it, but during Z-MODE, a PE only sees the
instructions assigned to it.

      As all PEs see all instructions in E-MODE, each PE can create
the Z-CODE it will require to re-execute the Segment as a Z-Segment,
the Z-CODE being stored in the Z-CACHE, and associated with
instructions in the Z-CODE are S-LISTS and D-LISTS as appropriate.
An S-LIST instructs the PE, in the Z-MODE, that one or more of the
source registers in an instruction assigned to it is set by another
instruction that is executed on another PE, an S-LIST is a receiving
obligation.  The D-LIST instructs the PE in the Z-MODE as to the
names of PEs that require the values of the register(s) that are
being set by an instruction that is assigned to it.  A D-LIST entry
is a sending obligation.

      The SFLA, STORE/FETCH LOOK-ASIDE, creates an alternate
execution path of the FETCH instructions in the presence of a valid
look-aside entry.  The SFLA is the set of STORE/FETCH bypass
registers, each having a BXD or an address mode of access, that can
be used as a search argument.

      In a conventional processor, which is pipelined, honoring a
fetch from a pending store buffer can be performed when the
implications vis a vis MP can be resolved.  The pending store buffer
becomes in essence a STORE/FETCH LOOK-ASIDE that provides a form of
registers from which the FETCH gets its data.  In essence, the FETCH
becomes an LR from an unarchitected register.

      To accomplish the same thing in MSIS it is necessary that the
STORE and FETCH be scheduled on the same processor, during the
E-MODE, based on both having the same address and being scheduled
sufficiently closely that the STORE would delay the FETCH if they
were on different Processing Elements (PEs).

      The difficulty in assigning instructions to PEs is that all PEs
must be aware of the assignment and if the assignment depends on
state information, such as address of access, each processing element
has to be able to generate all addresses.  In MSIS only the
processing element that executes the instruction needs to be able to
generate the address of the access and this reduces the number of
messages between PE to the minimum.  Further, the decision on the
scheduling of the FETCH needs to precede the generation of its
address in such a system.  The manner in which all this can be
accomplished is...