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MSIS Handling S/370 Serialization in MSIS without Delay

IP.com Disclosure Number: IPCOM000103734D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 187K

Publishing Venue

IBM

Related People

Frey, B: AUTHOR [+4]

Abstract

MSIS (Multisequencing a Single Instruction Stream) is a uniprocessor organization in which a set of processing elements (PEs) working in concert execute Segments of the instruction stream. The Segments are either P-Segments, normal uniprocessor instruction stream portions, that are processed in the E-MODE of MSIS and produce Z-Segments, or the Z-Segments that are processed in Z-MODE by MSIS. The main difference between E-MODE and Z-MODE is that during E-MODE each PE sees all instructions in the Segment and executes the ones that are assigned to it, but during Z-MODE, a PE only sees the instructions assigned to it.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

MSIS Handling S/370 Serialization in MSIS without Delay

       MSIS (Multisequencing a Single Instruction Stream) is a
uniprocessor organization in which a set of processing elements (PEs)
working in concert execute Segments of the instruction stream.  The
Segments are either P-Segments, normal uniprocessor instruction
stream portions, that are processed in the E-MODE of MSIS and produce
Z-Segments, or the Z-Segments that are processed in Z-MODE by MSIS.
The main difference between E-MODE and Z-MODE is that during E-MODE
each PE sees all instructions in the Segment and executes the ones
that are assigned to it, but during Z-MODE, a PE only sees the
instructions assigned to it.

      As all PEs see all instructions in E-MODE, each PE can create
the Z-CODE it will require to re-execute the Segment as a Z-Segment,
the Z-CODE being stored in the Z-CACHE, and associated with
instructions in the Z-CODE are S-LISTS and D-LISTS as appropriate.
An S-LIST instructs the PE, in the Z-MODE, that one or more of the
source registers in an instruction assigned to it is set by another
instruction that is executed on another PE, an S-LIST is a receiving
obligation.  The D-LIST instructs the PE in the Z-MODE as to the
names of PEs that require the values of the register(s) that are
being set by an instruction that is assigned to it.  A D-LIST entry
is a sending obligation.

      The LC or Level of Conditionality is essentially the number
branches, entry points, and serializers, that precede a given
instruction.  A recovery to an LC is attempted when branch has been
guessed incorrectly and a wrong putative instruction stream has been
pursued or a recovery from a serializer is required.  Recovery is
done through a ZZT-FRAME which monitors the registers changed at each
LC and via a scanning mechanism established the correct machine
state.  In the case of failed serialization a similar recovery is
required.  To avoid the effects of partial branch groups that arise
when an entry into a Z-SEGMENT is within a branch group, these entry
point can also increment the LC of the instructions which follow
them.  Adding LC classes does not alter the operation of the state
recovery as recovery is always made to the LC of the branch or
serializer that needs such recovery.  At the conclusion of a
Z-SEGMENT or at the point of a Branch Wrong Guess, the register state
of the processor is distributed among the register files that
constitute the results processing the Z-CODE.  To determine the
machine state a ZZT is employed.  The ZZT is a two-dimensional
structure which is accessed by both architected register name and
level of conditionality.  The level of conditionality of an
instruction is assigned to instructions during the E-MODE and
corresponds to the number of: branch instructions, serializers, and
entry points that are not targets of branches within the Z-CODE, that
precedes the instruction in the program segment.  Each position
within the ZZT ha...