Browse Prior Art Database

Self Prioritizing Multi-dropped Interrupt Acknowledge Mechanism

IP.com Disclosure Number: IPCOM000103741D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 6 page(s) / 241K

Publishing Venue

IBM

Related People

Welbon, EH: AUTHOR

Abstract

This article describes a self prioritizing interrupt identification mechanism which allows one of several processing unit peers to satisfy (i.e., respond to) an interrupt from a group of interrupt presenters. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 28% of the total text.

Self Prioritizing Multi-dropped Interrupt Acknowledge Mechanism

       This article describes a self prioritizing interrupt
identification mechanism which allows one of several processing unit
peers to satisfy (i.e., respond to) an interrupt from a group of
interrupt presenters.

                            (Image Omitted)

      The following benefits are provided by this mechanism.
1.  Single bus cycle resolution of interrupt ID from several
interrupters sharing a single interrupt input.
2.  Automatic hardware vectoring of acknowledging master.
3.  Software compatibility with existing systems.
4.  Support of up to 256 interrupt vectors with existing bus signal
count.
5.  No performance degradation of any other bus transactions.
6.  Minimum amount of hardware required.
7.  Hardware compatibility of vectored interrupt sources with
nonvectored interrupt sources on same interrupt input line.
8.  Lock-out free.

      This mechanism relies on the expansion of the meaning of
certain signals of the Micro Channel* bus.  A point by point
description of the mechanism follows.

      The sequence starts through the posting of an interrupt on the
Nth interrupt request line, IRQ(N).  Those bus masters that are
eligible to service IRQ(N) arbitrate for bus mastery in the usual way
by posting priorities on the -ARB bus.

      However, rather than a priority for memory, the priority that
is posted on the -ARB bus by the contending prospective interrupt
servers is the priority with which the server may service the
interrupt.  The priority may indeed be best thought of as a
preference code.  In this way, from a group of servicing elements a
preferred element is selected in one arbitration cycle.

      When some eligible master gains control of the bus a secondary
or interrupt response arbitration ensues.  The purpose of this
secondary arbitration is to decide which of the group of eligible
interruption sources are to be serviced by the prevailing interrupt
servicing element.

      Upon completion of the secondary arbitration, two parties will
have been selected.  These parties are,
(1) One of several interrupters at level IRQ(N).
(2) One of several servicing entities eligible to service an IRQ(N)
interrupt.

      On the completion of the secondary arbitration, the selected
interrupter presents an interrupt vector on the DATA bus.  The
prevailing interrupt servicing processor intercepts this vector from
the bus and uses it as a pointer into a table of interrupt response
routines in the usual way.

      This mechanism allows for three different levels of
prioritization; they are:
(1) IRQ Signal prioritization:  A device may be at any one of 16
different interrupt priority levels, IRQ(0) to IRQ(15).
(2) Interrupt Service Entity prioritization: Any one of 16 entities
may compete for the privilege of servicing the highest priority IRQ.
(3) Interrupt Request prioritization: Any one...