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Browse Prior Art Database

Video Controller Enable Registers in a Programmable System

IP.com Disclosure Number: IPCOM000103750D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 55K

Publishing Venue

IBM

Related People

Clarke, GL: AUTHOR [+4]

Abstract

Disclosed is a feature of an I/O controller for generating a VIDEO ENABLE signal to enable video memory and video I/O addresses during a power-on sequence. This feature allows the I/O controller to issue this signal to video controllers not having the capability of generating this signal. Since this feature is installed in a programmable system, this feature may be enabled or disabled during setup to avoid bus conflict when a video controller includes its own enable circuits. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 77% of the total text.

Video Controller Enable Registers in a Programmable System

      Disclosed is a feature of an I/O controller for generating a
VIDEO ENABLE signal to enable video memory and video I/O addresses
during a power-on sequence.  This feature allows the I/O controller
to issue this signal to video controllers not having the capability
of generating this signal.  Since this feature is installed in a
programmable system, this feature may be enabled or disabled during
setup to avoid bus conflict when a video controller includes its own
enable circuits.

                            (Image Omitted)

      Each bit in Port 94H enables or disables a group of addresses
100H through 107H, which permit the setup of various devices internal
or external to the I/O controller chip.  When the system unit is
turned on, a Power On Reset (POR) signal sets all of the bits in Port
94H to a one level, disabling the setup addresses.  This POR signal
also sets Bits 0 of Port 104H to a zero level, and Bit 1 of
Port 104H to a one level, disabling the functions of these bits.
Furthermore, the POR signal sets Bits 0 of Registers 3C3H and 102H to
zero levels, so that the VIDEO ENABLE signal provided as an output of
NAND gate 10 is held at a high level, which is a disabled condition.

      As power-on sequencing continues, Bit 6 of Port 94H is set to
zero, enabling Port 104H.  Then Bit 0 of Port 104H is set to a one
level, providing a signal to enable Register 102H...