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Zero Cell Tie Up/Down Books for VLSI ASIC

IP.com Disclosure Number: IPCOM000103811D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Hedman, RL: AUTHOR [+2]

Abstract

ASIC CMOS/BiCMOS technologies contain a library of logic functions. Since there are many possible logic functions, it is almost impossible for the circuit designers to provide all of these functions in the library. Instead, the library is designed with larger functions. If a function is not needed, the unused inputs are required to be tied to Vdd or GND. Traditionally, this approach requires a tie-up and a tie-down circuit to the library and also reduces the chip density due to the extra circuits required and the wires needed to connect the tie up/down circuits to the unused inputs. Another approach is to design the circuits to allow the unused inputs to be droppable. This approach makes the designs very complicated, and it takes longer to design. It is also more difficult to verify the integrity of the designs.

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Zero Cell Tie Up/Down Books for VLSI ASIC

      ASIC CMOS/BiCMOS technologies contain a library of logic
functions.  Since there are many possible logic functions, it is
almost impossible for the circuit designers to provide all of these
functions in the library.  Instead, the library is designed with
larger functions.  If a function is not needed, the unused inputs are
required to be tied to Vdd or GND.  Traditionally, this approach
requires a tie-up and a tie-down circuit to the library and also
reduces the chip density due to the extra circuits required and the
wires needed to connect the tie up/down circuits to the unused
inputs.  Another approach is to design the circuits to allow the
unused inputs to be droppable.  This approach makes the designs very
complicated, and it takes longer to design.  It is also more
difficult to verify the integrity of the designs.

      The conventional tie up/down books are usually designed with
poly or M1 LSTs which are connected to Vdd or Gnd buses.

      Described is a method to build the tie up/down circuit without
taking any silicon area.  Since all circuits have the Vdd and Gnd
buses going through their areas, it is possible to put the tie
up/down functions into the circuits by putting extra output LSTs
right on top of the Vdd and Gnd buses.  These output LSTs will be
used as the tie up/down functions for the unused inputs of these
books.  Therefore, the extra tie up/down books are eliminated.

      Sin...