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# Cyclic Redundancy Code Computation for a Variable Length Data

IP.com Disclosure Number: IPCOM000103822D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 89K

IBM

## Related People

Barucci, G: AUTHOR [+5]

## Abstract

Disclosed is a method to compute the Cyclic Redundancy Code (CRC) value in ONLY one clock pulse for a data the length of which stretches from one up to 8 bits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Cyclic Redundancy Code Computation for a Variable Length Data

Disclosed is a method to compute the Cyclic Redundancy Code
(CRC) value in ONLY one clock pulse for a data the length of which
stretches from one up to 8 bits.

The CRC computation of the cyclic redundancy code (CRC) of a
bit stream is usually performed with the help of a Linear Feedback
Shift Register LFSR which is a shift register with some Exclusive OR
based feedback logic in order to represent the CRC generator
polynomial.  The data bits are serially entered into this LFSR;
therefore, each bit of data requires one clock pulse to be pushed
into the register.

At the end of the operation, i.e., when all the data bits have
been entered into the LFSR, this last one contains the CRC value
corresponding to the entered data.

The main drawback of this method is that the computation time
takes as many clock pulses as there are bits of data which could not
be acceptable from a performance point of view.

This method may be extended for a data length greater than 8.

The data is received one byte at a time and the corresponding
CRC is computed by using a parallel process which is purely
combinatorial.

The logical inputs of this parallel process are the data byte
(8 bits) and the previous CRC value (16 bits in the example).

The combinatorial process, using the above inputs, comes out
from the equation of the polynomial generating the CRC.  The
equations, implemented by the combinatorial logic when the generator
polynomial Xsup 16+ Xsup 12+ Xsup 5+ 1 is used, are as follows :

X0,X1,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,X13,X14,X15,X16 are
the bits of the previous CRC

Y0,Y1,Y2,Y3,Y4...