Browse Prior Art Database

High Performance DMA Controller/CPU Interface Mechanism

IP.com Disclosure Number: IPCOM000103848D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 111K

Publishing Venue

IBM

Related People

Kravitz, JK: AUTHOR [+2]

Abstract

In most current microprocessor based Communication systems, the CPU overhead of handing DMA controller operations has not been considered significant; however, in the emerging world of very high bandwidth communications, this overhead can lead to severely reduced communication throughput. The invention provides a method of interfacing a DMA controller, which is responsible for controlling the movement of data between the communications medium and CPU memory, and the CPU itself. This method reduces the CPU overhead for DMA controller management, as well as management of the memory buffers used by the DMA and the CPU.

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High Performance DMA Controller/CPU Interface Mechanism

      In most current microprocessor based Communication systems, the
CPU overhead of handing DMA controller operations has not been
considered significant; however, in the emerging world of very high
bandwidth communications, this overhead can lead to severely reduced
communication throughput.   The invention provides a method of
interfacing a DMA controller, which is responsible for controlling
the movement of data between  the communications medium and CPU
memory, and the CPU itself.  This method reduces the CPU overhead for
DMA controller management, as well as management of the memory
buffers used by the DMA and the CPU.

      The mechanism consists of two so-called Queue FIFOs
(FIRST-INFIRST-OUT), a commercially available electronic device for
each direction of data movement (i.e. Communication-line to memory,
and memory to communication line), thus totalling 4 separate Queue
FIFO's.

      For each of the two directions of travel, there is a Work Queue
FIFO, and a Completion Queue FIFO.

      For the direction Memory-to-Communication Medium (for brevity
this will be referred  to as the Transmit direction), the Work Queue
FIFO contains entries for data items that the CPU wishes to transmit
on the communication medium.   The entries are created by the CPU
(probably by software) and are removed by the DMA controller.  The
Completion Queue FIFO contains entries for each of the data items
transmitted via the DMA controller to the communication medium,
(i.e.the work completed by the DMA controller).  Each of these
entries is created by the DMA controller, and removed by the CPU.

      For the direction Communication Medium-to-Memory (for brevity,
referred to as the Receive direction), the Work Queue FIFO contains
entries representing free (unused) buffer areas in memory that can be
filled by the DMA controller with received information.  These
entries are created by the CPU and removed by the DMA controller as
needed.  The Completion Queue FIFO entries contain information about
actual data items received by the Communication Medium and
transferred by the DMA controller to buffer memory (i.e., the work
completed by the DMA controller for the Receive direction).  These
entries are created by the DMA controller and removed by the CPU.

The entries in the 4 Queue FIFOs contain at least the following
information.

o   The Receive direction Work Queue FIFO Entries contain

o   The memory address of a free buffer

o   The size of the buffer (optionally)

The Receive direction Completion Queue FIFO Entries contain:

o   The memory address of the filled buffer

o   The size of the received data item

o   The completion status (e.g. successful, error) of the DMA
    operation.

The Transmit direction Work Queue FIFO entries contain:

o   The memory address of a buffer of data to be transmitted

o   The size of the data to be transmitted

The Transmit dir...