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Browse Prior Art Database

High Coverage Three-Pattern DRAM Test

IP.com Disclosure Number: IPCOM000103882D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Haselhorst, KH: AUTHOR [+3]

Abstract

Disclosed is a combined address and data main store test. This is a high speed high coverage DRAM test. It can be used for testing at IPL time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

High Coverage Three-Pattern DRAM Test

      Disclosed is a combined address and data main store test.  This
is a high speed high coverage DRAM test.  It can be used for testing
at IPL time.

DRAM DECODE AND ADDRESSING TEST (DDAT)

      This is the unique part of this test.  By using three sets of
diagonal patterns, address tests, and data tests are combined.  This
simplifies the testing and greatly increases the speed.  An example
chip is shown for clarity; however, any size chip can be tested with
this method.  The first two patterns do most of the testing.  The
third is used to check the internal decoding of the DRAMs as most
chips are broken into many small arrays internally.

      This test will, in essence, write a diagonal of bits through
each array module.  This will test each RAS and CAS decode within the
chips and also check the addressing lines to the chips for stucks and
for shorts between address lines.

      Test patterns for 12-10 16Mb modules are depicted in Fig. 1.
The '/' are the same value as '\' for any pattern, they are always
different than the'.'.

1.  All of Main Store will be written to '1'b

    This includes all data bits, redundant bits, checkbits, and
    usable tags.

2.  Write pattern 1 (diagonal of '0'b)

The diagonal pattern of zeroes will be written in each 1/4 chip as
shown in the previous diagrams.  This can be done by a series of
subroutine calls.  Each subroutine call will write a 1K by 1K piece
on each module for the example depicted in Fig. 2.  The subroutines
are:

UR to LL:    Write Diagonal from Upper Right to Lower Left
UL to LR:    Write Diagonal from Upper Left to Lower Right
SmallURLL:   Write Diagonal in all 64x64 pieces from UR to LL
SmallULLR:   Write Diagonal in all 64x64 pieces from UL to LR

3.  Wait for two times the refresh length to allow decay.

4.  Read all of Main Store

    All of main store will be checked for the correct data.  All
    errors in any bit will be encoded and stored for analysis later.

5.  Write all of main store to 0's

6.  Write pattern 2 (diagonal of '1'b)

    This is done the same way as pattern 1 except the subroutine
    calls are invoked passing a value to store '0'b.

7.  Wait for two times the refresh length to allow decay

8.  Read all of Main Store

    All of main store will be checked for the correct data.  All
    errors in any...