Browse Prior Art Database

High Performance Dual Architecture Processor

IP.com Disclosure Number: IPCOM000103884D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 142K

Publishing Venue

IBM

Related People

Flurry, GA: AUTHOR [+2]

Abstract

Disclosed is the IBM RISC/CISC, a unique processor that exhibits exter- nally two major architectures. It can appear as:

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This is the abbreviated version, containing approximately 39% of the total text.

High Performance Dual Architecture Processor

      Disclosed is the IBM RISC/CISC, a unique processor that
exhibits exter- nally two major architectures.  It can appear as:

o   A high performance Reduced Instruction Set Computer (RISC) This
    Native manifestation of the RISC/CISC provides the typical RISC
    concepts of a User Mode and Privileged Mode.

o   The CISC manifestation is a 100% compatible emulation of an
    industry standard CISC processor provided by a combination of
    hardware and microcode; the microcode uses the Native
    architecture, plus extensions, to emulate the CISC.  The
    RISC/CISC emulation performs at least as well as the real
    industry standard processor.

      The RISC/CISC processor provides the ability to run software
compatible with both aspects of the processor.  Thus, it provides a
migration path from the CISC environment to the RISC environment.  It
does so without software emulation of a CISC processor by a RISC
proces- sor, a solution with severe performance problems.

The important aspects of the RISC/CISC are:

o   Full 32-bit architecture

o   64, 32-bit General Purpose Registers (architecturally)

o   Several Special Purpose Registers

o   Pipelined instruction processing

o   Internal instruction and data cache

o   Virtual memory support

o   Demand paging support

o   Translator for CISC emulation

o   Internal ROS for CISC emulation

The figure shows a block diagram of the RISC/CISC.  It contains the
following major components:

o   MMU - The Memory Management Unit contains various registers and
    control logic for virtual to real address translation and cache
    management.

o   Cache Unit - The cache unit contains a small on-chip cache, cache
    tags for a larger, off-chip cache and cache management logic.

o   CISC Instruction Buffer - The CISC Instruction Buffer accepts
    instruction fetch results, and allows sophisticated manipulation
    of the information in the buffer to facilitate CISC instruction
    decoding.

o   CISC Decode and Translate Unit - The CISC Decode and Translate
    Unit decodes the data in the CISC Instruction Buffer into
    complete CISC instructions, and then translates the instruction
    into:

        a Native instruction - the only instruction, or the first
        instruction of a sequence required to implement the CISC
        instruction
        a ROS address - for the rest of an instruction sequence, if
        any
        CISC data - from various CISC instruction fields, and state
        information kept by the Translation Unit, both used by subse-
        quent units to implement CISC instructions

o   CISC Instruction Fetch Unit - The CISC Instruction Fetch Unit is
    responsible for calculating CISC instruction addresses and
    fetching CISC instructions.

o   ROS - The ROS contains instructions for i...