Browse Prior Art Database

Method for Masking Unpredictable Shift Register Latch States During Random Pattern Self-Test

IP.com Disclosure Number: IPCOM000103887D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Kaliszewski, KT: AUTHOR

Abstract

A method for masking unpredictable shift register latch (SRL) states during random pattern self-test (RPST) is disclosed. A latch in a scan ring that has the potential of taking on an unpredictable value has its data forced to a known value before it is used to build a signature. This is accomplished by scanning the test data out of the device under test, modifying it where necessary, and restoring it into the device under test via scanning. Once the unpredictable value has been forced to a known value, a self-test signature can be built.

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Method for Masking Unpredictable Shift Register Latch States During Random Pattern Self-Test

      A method for masking unpredictable shift register latch (SRL)
states during random pattern self-test (RPST) is disclosed.  A latch
in a scan ring that has the potential of taking on an unpredictable
value has its data forced to a known value before it is used to build
a signature.  This is accomplished by scanning the test data out of
the device under test, modifying it where necessary, and restoring it
into the device under test via scanning.  Once the unpredictable
value has been forced to a known value, a self-test signature can be
built.

      Random Pattern Self-Test (RPST) is used to verify internal
combinatorial logic on a chip.  RPST normally requires that the state
of every SRL (Shift Register Latch) in an LSSD scan ring be
predictable (given some initialization conditions) because these
values are collected and compressed in a Linear Feedback Shift
Register (LFSR) called a Multiple Input Signature Register (MISR) or
Single Input Signature Register (SISR) (see the figure).  The value
collected in the MISR is called a signature.  If some of the SRLs in
the scan ring take on unexpected values (possibly due to timing or
design problems), RPST will generate a failing signature and report
the Device Under Test (DUT) as failing.

      The 'Method for Masking Unpredictable SRL States During RPST'
allows RPST to be run even if the DUT contains latches that have the
potential of taking on unknown values.  This is accomplished by
'masking off' or forcing the state of the unpredictable SRLs to a
known logic level (1 or 0).  In this way, every value used in
creating a signature will be consistent and predictable.

      The figure shows a basic hardware configuration for RPST.

      Source test data is created by the PseudoRandom Pattern
Generator (PRPG).  The test (cycling of test clocks) is performed by
the clock and scan control hardware.  The MISR collects the test
data.  This  method  for masking  unpredictable  states  has one
major difference from typical RPST procedures.  The difference is,
once the test clocks are cycled, the data  is removed from the chip,
modified, and restored into the chip.  Then, after the data has been
modified, the MISR is allowed to collect and compress it into a
signature.  Details of this process follow.

      Control logic initialization is unchanged from normal self-test
procedures as is the scan ring initialization.  The important
dif...