Browse Prior Art Database

Asynchronous Data Sampling Technique Utilizing Dual Gated Oscillators with Passive Delay Lines

IP.com Disclosure Number: IPCOM000103891D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 178K

Publishing Venue

IBM

Related People

Georgiou, CJ: AUTHOR [+4]

Abstract

Disclosed is a method of adjusting the phase of a local clock with respect to an incoming asynchronous data bit-botream without requiring "synchronization" bits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Asynchronous Data Sampling Technique Utilizing Dual Gated Oscillators with Passive Delay Lines

      Disclosed is a method of adjusting the phase of a local clock
with respect to an incoming asynchronous data bit-botream without
requiring "synchronization" bits.

      Asynchronous or self-timed data transfer is necessary for data
rates higher than several hundred MHz, because synchronous data
transfer requires clock signals to be distributed across a system
with accurate phases and, thus, become difficult to realize at such
data rates.  However, implementing a fast and reliable asynchronous
data transfer is still a difficult problem because there is no fixed
phase relation between the transitions of the arriving data signal
and the transitions of the local clock.

      Conventionally, a phase-lock loop (PLL) or a Surface Acoustic
Wave (SAW) filter is used to extract the clock from the incoming data
signals, and the extracted clock is then provided to the receiving
data latch for sampling the data.  The problem with this scheme is
that a PLL usually requires a number of bits before it is both
frequency and phase locked to the incoming data.  Depending on the
design technique used, the number of bits needed to achieve PLL
synchronization can range from under 100 to 1000's, thus,
significantly increasing the latency of the data transfer.  In
contrast, the disclosed method can adjust the clock phase with
respect to the data without requiring synchronization bits.

      The essence of this disclosure is to utilize a gated
oscillator, which is periodically "tuned" to a fixed frequency
reference, while another identical gated oscillator is used to sample
the data to assure no disruption of data sampling when the gated
oscillator is "tuned." The switch of oscillators occurs at convenient
times in the data trans- fer, e.g., between frames.  The frequency of
the oscillator change-over could be in the order of hundreds of
microseconds to minimize data rate drift effects due to thermal
variations.  The actual tuning is done with a PLL circuit, which
provides a digitally-controlled analog signal to set the delay of a
string of inverters that determine the clock frequency.  When not
being tuned, the digitally-controlled analog signal remains fixed
until the ring oscillator is re- inserted in the PLL loop.  Finally,
both of the incoming data signals and the PLL reference frequency are
synthesized from the same lower frequency reference.

      The gated ring oscillator is triggered by the first data
transition.  Appropriate fixed delay blocks are inserted between the
output of the ring oscillator and the clock input of the latch to
align the middle of the data pulse with the leading edge of the gated
oscillator, as illustrated in Fig. 1.  The transition
detect-and-store function, shown in Fig. 2, detects the first data
transition, stores the result and provides a positive going enable
signal to the gated oscillator.

    ...