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Instruction Address Compare using Memory Flags

IP.com Disclosure Number: IPCOM000103895D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Knipfer, DL: AUTHOR [+2]

Abstract

A method of allowing a large number of instruction address compare stops to be set in a system without using the conventional methods of instruction checkpointing (replacing the existing instruction with a special supervisor call) or by using special compare registers to compare for preset instruction addresses is disclosed. The method, using either a special error correction code (ECC) encode in main storage (MS) or special main storage TAG bits, allows the processor to run at its rated speed except in the very near proximity of an instruction address which has a stop set. The method also allows controlled notification of an instruction address compare stop occurrence to a service processor, to any task encountering the instruction address, or to only a specific task when it encounters the instruction address.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Instruction Address Compare using Memory Flags

      A method of allowing a large number of instruction address
compare stops to be set in a system without using the conventional
methods of instruction checkpointing (replacing the existing
instruction with a special supervisor call) or by using special
compare registers to compare for preset instruction addresses is
disclosed.  The method, using either a special error correction code
(ECC) encode in main storage (MS) or special main storage TAG bits,
allows the processor to run at its rated speed except in the very
near proximity of an instruction address which has a stop set.  The
method also allows controlled notification of an instruction address
compare stop occurrence to a service processor, to any task
encountering the instruction address, or to only a specific task when
it encounters the instruction address.

      A main storage TAG bit is defined for each quadword of main
storage.  To set an instruction address compare, a TAG bit of the
quadword containing the instruction is set to inform the hardware
that an instruction address compare is pending.  An entry is made to
a table maintained in main storage which contains the instruction
compare address and an indication of whether a specific task, any
task, or the service processor is to be notified when an instruction
address compare occurs.  The maintenance and use of the table is done
by code while under the protection of a lock, thus providing atomic
update to the table.

      When the instruction quadword containing the MS TAG bit is
fetched, an exception trap is taken so that the Instruction Address

Register (IAR) can be compared to a table of instruction addresses
that have compares set.  If the instruction addresses match and the
service processor is to be notified, a command is sent to the service
processor indicating that the instruction address compare has
occurred.  If the instruction addresses match and any using task is
to be notified or the current ta...