Browse Prior Art Database

Delayed Multiple-Bit Error Detection for Parity-Constrained Channels

IP.com Disclosure Number: IPCOM000103901D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Coppersmith, D: AUTHOR [+2]

Abstract

Disclosed is a method for detecting multiple bit errors on channels which are constrained to transmit blocks of data with too few parity-check bits per block for standard error detection schemes to succeed. The invention is best described by example of a preferred embodiment, designed for a machine that will pass data blocks each consisting of 96-bits, 92 information bits and 4 parity bits. The data blocks are labeled B sub j, the indexing reflecting their relative times of transmission. The code will detect any random 2-bit error and any burst error of length at most 8 occurring in any two consecutive blocks B sub j %, % B sub with j odd. These errors may not necessarily be detected immediately after the second block B sub is received, but certainly will be detected after block B sub is received.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Delayed Multiple-Bit Error Detection for Parity-Constrained Channels

      Disclosed is a method for detecting multiple bit errors on
channels which are constrained to transmit blocks of data with too
few parity-check bits per block for standard error detection schemes
to succeed.  The invention is best described by example of a
preferred embodiment, designed for a machine that will pass data
blocks each consisting of 96-bits, 92 information bits and 4 parity
bits.  The data blocks are labeled B sub j, the indexing reflecting
their relative times of transmission.  The code will detect any
random 2-bit error and any burst error of length at most 8 occurring
in any two consecutive blocks B sub j %, % B sub <j+1> with j odd.
These errors may not necessarily be detected immediately after the
second block B sub <j+1> is received, but certainly will be detected
after block B sub <j+2> is received.  The code is essentially a BCH
code; the novelty is that transmission of the parity bits are
delayed.  The procedure for interleaving of the data bits with the
data bits is such that the system constraints are met and that the
delay between reception of the data bits and the decision whether or
not errors are made is relatively short.  No attempt is made to
correct the errors.

      In the preferred embodiment, the j-th "code-block" consists of
the following:  the first 92 bits of B sub <2j-1>, which are data
bits, the first 92 bits of B sub <2j>, which are data bits, the last
4 bits of B sub <2j>, which are check bits, and the last 4 bits of B
sub <2j+1>, which are check bits.

      Sender.  For transmission of the j-th "code-block" all 8 bits
 e sub m , %% 1 le m le 8 of an 8-bit accumulator are set to 0. ...