Browse Prior Art Database

Alternative Implementation for Phase Buffer in Quasi-Synchronous Interface

IP.com Disclosure Number: IPCOM000103917D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 6 page(s) / 215K

Publishing Venue

IBM

Related People

Ruedinger, JJ: AUTHOR

Abstract

Disclosed is an implementation of a phase alignment buffer which is well suited for VLSI implementation since it does not require the use of delays, clock sampling, or data sampling.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 23% of the total text.

Alternative Implementation for Phase Buffer in Quasi-Synchronous Interface

      Disclosed is an implementation of a phase alignment buffer
which is well suited for VLSI implementation since it does not
require the use of delays, clock sampling, or data sampling.

      The disclosed phase buffer avoids the use of delays, but it
introduces the possibility of a "glitch" where the data coming out of
the phase buffer can be invalid for one cycle some time after the
circuit is initialized.  Even though the timing of when the glitch
can occur is unpredictable, it is guaranteed to only occur once after
the system is initialized.  If the receiving circuit is capable of
handling an interrupted data stream, then this glitch will not create
a problem.

      Since this design deals with passing information across two
different clock boundaries, the issue of metastability must be
addressed.  For the purposes of this discussion, it is assumed that
there exists for any particular VLSI technology a circuit which will
not transmit a metastable state caused by crossing a clock boundary.
The value transmitted can be incorrect; it is only required to be a
stable logic value (0 or 1 in a binary logic system).  This circuit
can be a single latch or gate, or a combination of either latches or
gates; the only property required is that a metastable voltage level
not be propagated.

      (A metastable state is defined here as being a voltage level
which is read by a binary latch as an undefined value, not a valid 0
or 1.  This undefined voltage level can then produce a similar
undefined value at the output of this binary latch.  In some VLSI
technologies, a metastable condition can occur when the "clock
trigger" input of a latch closes just as the data input changes.  The
output of the latch can be a voltage that is in the undefined range
between a solid 0 and 1.  If this undefined voltage level persists
long enough, it can trigger other latches to produce undefined
voltages as well.  A common technique to reduce the probability of
this happening to almost zero is to run the output of the first latch
which is capturing data across a clock domain into a second latch
before using the information.  The output of the second latch can
then be considered to be stable.)  For the purposes of the following
discussion, it is assumed that only one latch is needed to insure a
stable, although not necessarily correct, output value when its input
comes from a different clock domain.  The design being disclosed
herein would still hold if more than a single latch level were
required to insure a stable output level; however, some adjustments
may need to be made.

      Using the assumption that a single latch followed by a logic
gate will insure that stable data is captured correctly across a
clock boundary, the driving signal on the sending clock must be sure
to hold its value for at least 2 consecutive (receiving latch clock)
cycles each time it c...