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Browse Prior Art Database

Pipeline Apparatuses for Shared Level-Two Caches

IP.com Disclosure Number: IPCOM000103925D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Horvath, T: AUTHOR [+3]

Abstract

Disclosed is a multiprocessor (MP) system in which each processor has a level-one (L1) cache and a cluster of processors share a level-two (L2) cache. Having an L2 cache shared by a number of L1 caches (or CPUs) is an important MP feature for both cost and performance, but its major concern is the access delay when the cache is simultaneously accessed by several processors. Unlike an L1 cache to which the CPU accesses are in a small unit of one or two words, accesses to the L2 cache are on an L1 line basis. Therefore, when the L2 is serving a processor's L1 cache miss, a second L1 cache miss from other processor has to wait until the first missed line is sent out of the L2.

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This is the abbreviated version, containing approximately 52% of the total text.

Pipeline Apparatuses for Shared Level-Two Caches

      Disclosed is a multiprocessor (MP) system in which each
processor has a level-one (L1) cache and a cluster of processors
share a level-two (L2) cache.  Having an L2 cache shared by a number
of L1 caches (or CPUs) is an important MP feature for both cost and
performance, but its major concern is the access delay when the cache
is simultaneously accessed by several processors.  Unlike an L1 cache
to which the CPU accesses are in a small unit of one or two words,
accesses to the L2 cache are on an L1 line basis.  Therefore, when
the L2 is serving a processor's L1 cache miss, a second L1 cache miss
from other processor has to wait until the first missed line is sent
out of the L2.  Assume that the number of bytes that can be
transferred from L2 to L1 is called the access unit, then the second
miss has to wait as many cycles as the ratio of the L1 line size to
the access unit.  For example, if the L1 line size is 32 bytes and
the access unit is 4 bytes, L2 needs a minimum of 8 cycles to serve
an L1 miss.

      Disclosed is a set of pipeline apparatuses for L2 such that the
cache can handle one L1 miss every cycle.  The idea is to allocate a
pipeline buffer to stage a line being loaded from L2 to an L1 such
that in the next cycle, the L2 is ready to accept another request.

      The figure contains an MP system with 2 CPUs, each one has an
L1 cache and the L1 caches are sharing the L2 cache.  Requests
(assume L1 cache misses) to the L2 are sent through bus B1.  A
request address is decoded to look up the cache directory and to
address data array at the same time.  If th...