Browse Prior Art Database

Shift Register Latch for AC, Delay or Transition Fault Testing at Chip, Multi-Chip Module or System Levels

IP.com Disclosure Number: IPCOM000103927D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Bossen, DC: AUTHOR [+2]

Abstract

This invention disclosure applies to the testing of AC, Delay or transition faults in semiconductor chip, multi-chip module or collection of modules. Delay testing requires a pair of patterns, an initialization pattern and a transition pattern. These patterns are applied to the SRLs and the primary inputs of the entity under test. In this disclosure a latch design is presented so that any arbitrary pair of patterns can be applied by scanning to all SRLs on the entity under test (chip or multi-chip module). Since there is no restriction on the pattern pairs that can be applied for delay test, the delay fault detection and isolation coverage is maximized. By using the AC SRLs presented here, test pattern pairs generated by any delay fault test pattern generator program or device can be applied to the entity under test.

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This is the abbreviated version, containing approximately 52% of the total text.

Shift Register Latch for AC, Delay or Transition Fault Testing at Chip, Multi-Chip Module or System Levels

      This invention disclosure applies to the testing of AC, Delay
or transition faults in semiconductor chip, multi-chip module or
collection of modules.  Delay testing requires a pair of patterns, an
initialization pattern and a transition pattern.  These patterns are
applied to the SRLs and the primary inputs of the entity under test.
In this disclosure a latch design is presented so that any arbitrary
pair of patterns can be applied by scanning to all SRLs on the entity
under test (chip or multi-chip module).  Since there is no
restriction on the pattern pairs that can be applied for delay test,
the delay fault detection and isolation coverage is maximized.  By
using the AC SRLs presented here, test pattern pairs generated by any
delay fault test pattern generator program or device can be applied
to the entity under test.  The latch design permits testing of L2 to
L1 system path per system timing requirements.

      The AC shift-register latch (AC SRL) is shown in Figure 1.  It
is made up of three latches: L1, L2 and L2H.  L1 is the standard LSSD
L1 latch.  L2 is a modified LSSD L2 latch.

The behavior of the L2 latch is as follows:

o   As in standard LSSD, the value of L2 latch is set to the value of
    the L1 latch when either the B or the C2 clocks is at 1.  Both B
    and C2 clocks are off when E clock is 1 and vice versa.  The
    value of L2 latch does not change when B, C2 and E each are 0.

o   The behavior of the L2H latch is as follows:

    -   The value of L2H latch is set to the value of the L2 latch
        when the H clock is at 1.  The value of L2H latch does not
        change when the H clock is 0.

    AC SRLs are connected to form a shift register as in standard
    LSSD.  Pins at chip and module level are assigned as usual for
    supplying the clocks to the SRLs and for scan data in and out.

    DELAY TESTING USING...