Browse Prior Art Database

Filtering EX Status in Multiprocessor Caches

IP.com Disclosure Number: IPCOM000103930D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed is a method of filtering the EX status, as used in multiprocessing (MP) cache applications, by providing a mechanism for determining, upon a cache miss, whether the line could be contaminated in a remote cache. The method is based on the conservative approximation of remote EX status.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Filtering EX Status in Multiprocessor Caches

      Disclosed is a method of filtering the EX status, as used in
multiprocessing (MP) cache applications, by providing a mechanism for
determining, upon a cache miss, whether the line could be
contaminated in a remote cache.  The method is based on the
conservative approximation of remote EX status.

      In certain MP environments it is beneficial to be able to
conveniently determine, upon a cache miss, whether the line is
contaminated at a remote cache.  For example, consider a common bus
type store-in an MP cache design.  If the bandwidth of the memory is
good enough to fetch a missed line into a cache and if the line is
not contaminated at a remote cache, normally such implementations
would require duplicated copies of the cache directories.  If such
duplication is to be avoided, it is desirable to be able to determine
whether a missed line is EX at the remote caches without
interrogating the remote cache directories.

      In prior art, approximations were made for the coverage of
lines in a cache via a hashed bit-vector.  The concept described
herein adopts similar techniques to approximate just the EX type
lines in a cache.  For each processor Psub i, a bit-vector Vsub i is
considered.  Each line L is hashed into a bit (Vsub i left lbracket L
right rbracket) of Vsub i via certain middle address bits.  The
management of Vsub i content is similar to the prior art concept, as
follows:

o   Initially all Vsub i vectors are zeroed.

o   When a line L obtains store authorization (e.g., EX status) at
    Psub i, the bit Vsub i left lbracket L right rbracket is turne...