Browse Prior Art Database

Planarized NVRAM Cell with Self-Aligned BL-BL and WL-BL Isolations

IP.com Disclosure Number: IPCOM000103937D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 77K

Publishing Venue

IBM

Related People

Acovic, A: AUTHOR [+4]

Abstract

Disclosed is a fully self-aligned and planarized NVRAM cell with dielectric-filled trench isolation between each bit line and field dielectric isolation between bit lines and word lines to achieve high density NVRAM chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Planarized NVRAM Cell with Self-Aligned BL-BL and WL-BL Isolations

      Disclosed is a fully self-aligned and planarized NVRAM  cell
with  dielectric-filled  trench  isolation  between each bit line and
field dielectric isolation between  bit  lines  and word lines to
achieve high density NVRAM chip.

      Because of non-self-aligned structures, the conventional NVRAM
cells can hardly achieve the maximal chip density allowed by
lithography.    The  double-poly  stacked gate  NVRAM  cells  also
create certain topography problems which jeopardize process and
device reliability.

      Disclosed is a fully self-aligned and planarized  NVRAM cell
with  self-aligned  trench isolation between bit lines and
self-aligned field dielectric  isolations  patterned  by
chemical-mechanical  polishing technique between word lines.  The key
invention is the following:

1.  Word lines (control gates - poly 2) are self-aligned  to field
    oxide (Fig. 2 A-A'), floating gates (poly 1 - Fig.  2 B-B'), and
    trench oxide (Fig. 2 B-B').

2.  Bit  lines  (source and drain) are self-aligned to field oxide
    (Fig. 2 C-C'), stack gate (Fig. 2 C-C') and trench oxide ( Fig. 2
    D-D').

3.  Floating gates (poly 1) are self-aligned to trench oxide (Fig. 2
    B-B'), word lines (control gates - poly 2,  Fig.  2 B-B'), bit
    lines (Fig. 2 C-C') and field oxide (Fig. 2 C-C').

4.  Field  oxide  (isolates  word lines WL) and trench oxide
    (isolates bit lines BL) are done  in  one  process  step (one
    oxide filled and polish, Fig. 1b)

5.  Use  multi-layer  depositions (Figs. 1a and 1b) together with
    chemical-mechanical polishing technique  to  define trench
    isolations  and  floating gates (no mask is need for these two
    steps; they are defined by word line  (WL) and bit line (...