Browse Prior Art Database

Method for Setting C2 Security Bit

IP.com Disclosure Number: IPCOM000103954D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Clarke, GL: AUTHOR [+4]

Abstract

Disclosed is a method for setting a C2 Security bit, during a Power On Setup (POS) sequence, using logic within an I/O controller chip config ured to be used in systems with and without C2 Security features.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 98% of the total text.

Method for Setting C2 Security Bit

      Disclosed is a method for setting a C2 Security bit, during a
Power On Setup (POS) sequence, using logic within an I/O controller
chip config ured to be used in systems with and without C2 Security
features.

      The Figure illustrates bits 5, 6, and 7 of Planar POS Port 94H
register 10 each enable or disable a group of addresses 100H through
107H, which permit the setup of various devices internal or external
to the I/O controller.  With the Power On Reset (POR) signal, all
bits in Port 94H register 10 come up at as logical ones, disabling
the setup addresses of the I/O controller.

      The video and C2 Security enable Port 104H register 12 can be
addressed in the I/O controller after Port 94H bit 6 has been set to
zero during the power on sequence.  Bit 7 of this register 12
provides the C2ENB signal, enabling C2 Security.  With the POR
signal, this bit comes up enabled, at a logical one level.  However,
in systems not having C2 Security, this bit is disabled during
further power on sequencing.

      When Program command logic 14, after bit 6 of Port 94H has been
set to zero, decodes an attempt to write to Port 104H, a clock signal
is provided to register 12, so that bit 7 is set according to the
data bit 7 signal on line 16, through OR circuit 18.  When this bit 7
is a logical zero, C2 Security is disabled.  The other input to OR
circuit 18 is provided so that bit 7 in register 12 will be reset
with the...