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Overview of a Microcoded I/O Sequencer

IP.com Disclosure Number: IPCOM000103969D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 124K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+3]

Abstract

One of the problems of implementing the RISC System/6000* architecture o a single chip is the amount of function to be included. Because of space limitations, a compromise had to be taken in order to retain the performance of the RISC System/6000 while fitting all of the logic onto a single chip. One way to accomplish this is to build a general purpose coprocessor that will execute all of the functions not already imple mented by the other execution units. This general purpose coprocessor is called the I/O Sequencer and its description follows.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Overview of a Microcoded I/O Sequencer

      One of the problems of implementing the RISC System/6000*
architecture o a single chip is the amount of function to be
included.  Because of space limitations, a compromise had to be taken
in order to retain the performance of the RISC System/6000 while
fitting all of the logic onto a single chip.  One way to accomplish
this is to build a general purpose coprocessor that will execute all
of the functions not already imple mented by the other execution
units.  This general purpose coprocessor is called the I/O Sequencer
and its description follows.

      The RSC design uses the I/O Sequencer, an internal processor,
to implement state-intensive Input/Output functions, such as TLB Miss
reload, data locking, and DMA.  In addition, the RSC uses the I/O
Sequencer for access to low utilization, special purpose registers.

Functional Blocks

The figure shows the overall structure of the I/O Sequencer data
path.

The I/O Sequencer consists of the following major blocks:

o   ROS - 3072 x 18 bits

o   Private RAM -96 locations of 32 bits each.  The PRAM contains a
    combination of architected, local and shadow registers, and
    temporary work area for the microcode

o   Sequencer GPRs--two banks of eight 32-bit registers.  One bank is
    associated with Instruction processing tasks, and the other bank
    is associated with Bus and Asynchronous tasks.

o   Control logic that executes the microcode, controls the flow of
    execution, prioritizes external events that effect the flow of
    execution, and interfaces to other parts of the RSC chip and the
    I/O chip

The tasks that are performed by the I/O Sequencer microcode are
broken up into three categories:

o   Instruction Processing.  These are tasks that are initiated by
    the fixed point unit, generally to access an architected register
    contained within the PRAM, to perform a PIO, to translate an
    address following a TLB miss, or error handling (DSI, ISI, PI,
    etc.).

o   Bus Processing.  These tasks are initiated by the I/O Sequencer
    afte its control logic determines that the Indus I/O chip
    requires servicing.  Bus processing tasks are associated with
    DMA.

o   Asynchronous Processing.  These tasks are initiated by the I/O
    Sequencer when its control logic detects an asynchronous event
    that requires servicing.  These include System Reset, Real Time
    Clock and Decrementer service routines, as well as ECC error
    recovery.

      When occurring simultaneously, Asynchronous traps are given the
highest priority, followed by bus processing, and then instruction
processing.

      The link registers retain the current ROS address when
execution is transferred from one task to another.  There are two
link registers:  one for instruction processing, and one for bus
processing.  Asynchro nous processing does not require a link
regi...