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Browse Prior Art Database

High Density Substrate Process Improvement

IP.com Disclosure Number: IPCOM000103977D
Original Publication Date: 1993-Feb-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 173K

Publishing Venue

IBM

Related People

Frankeny, RF: AUTHOR [+2]

Abstract

The disclosed process utilizes a modified reference plane foil which leads to identically shaped holes for reference plane vias and isolated vias in 1S1P (1 signal plane and 1 power or reference plane) substrate elements.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Density Substrate Process Improvement

      The disclosed process utilizes a modified reference plane foil
which leads to identically shaped holes for reference plane vias and
isolated vias in 1S1P (1 signal plane and 1 power or reference plane)
substrate elements.

      The reference plane foil has a structure as shown in Fig. 1,
where a copper/invar/copper (CIC) foil is clad on one side by chrome
and copper layers.  The chrome layer is very thin and acts as a
barrier during etching of either the CIC or copper layers.
Similarly, other barrier metals such as tin-nickel or titanium could
be used.

      Fig. 2 shows, a photoresist applied to both sides of a
reference plane foil, exposed to actinic energy through as mask, and
chemically developed to produce openings in the photoresist on one
side.

      Fig. 3 shows the result of chemically etching the foil in
Figure 2 with an etchant which is specific to the CIC layer.  The
foil retains the etch barrier metal layer but has a pattern of blind
clearance holes.

      After removal of the photoresist, a photoimageable dielectric
is applied under vacuum to the etched side of the reference plane
foil so that the etched clearance holes are completely filled with
the dielectric.  Subsequently, a controlled thickness of
photoimageable dielectric is applied to substrate.  The resultant
structure is shown in Fig. 4.

      Fig. 5 shows the result of exposing the dielectric to actinic
radiation through a mask (imaging) and developing chemically to
produce holes (vias) of uniform size and shape.  This is followed by
chemical removal of the etch barrier metal (chrome) at the base of
the photoimaged vias.

      Fig. 6 shows copper studs electroplated in the holes produced
in Figure 5.  Polishing or planarizing of the surface of the part
produces studs which are level with the dielectric surface.

      Fig. 7 shows the application and imaging of a photoresist to
allow etching of the bottom copper layer for studs which are to be
isolated from the groundplane.  Studs which are to...