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Segment Table Origin Control Mechanism for Expanded Virtual Addressing

IP.com Disclosure Number: IPCOM000104065D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Brenza, JG: AUTHOR

Abstract

Conventionally, many digital computers restrict virtual addressing to 31 bits (2GB's of byte addressable virtual space). Such computers allow multiple virtual space addressing by appending a tag to each different virtual space and its corresponding set of addresses. This tag is called a STO, or Segment Table Origin. In practical terms, the STO value is the origin address in real memory of a table of data which stores certain translation parameters for the corresponding virtual space. Cache subsystems store the STO tags and the virtual addresses in their directory arrays. Thus data from different virtual spaces may coexist in cache. For efficient cache data look-up operations, it is desirable to transmit the virtual address and the STO tag to the cache subsystem at about the same time.

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Segment Table Origin Control Mechanism for Expanded Virtual Addressing

      Conventionally, many digital computers restrict virtual
addressing to 31 bits (2GB's of byte addressable virtual space).
Such computers allow multiple virtual space addressing by appending a
tag to each different virtual space and its corresponding set of
addresses.  This tag is called a STO, or Segment Table Origin.  In
practical terms, the STO value is the origin address in real memory
of a table of data which stores certain translation parameters for
the corresponding virtual space.  Cache subsystems store the STO tags
and the virtual addresses in their directory arrays.  Thus data from
different virtual spaces may coexist in cache.  For efficient cache
data look-up operations, it is desirable to transmit the virtual
address and the STO tag to the cache subsystem at about the same
time.

      This article describes a control mechanism which improves cache
operation in a digital computer which implements expanded virtual
addressing.  The expanded virtual addresses are 64 bit binary
numbers.  Whenever a 64 bit virtual address is used, the low-order 31
bits still refer to a byte address within a 2GB virtual space.  The
high order 33 bits of the expanded virtual address are called an
ALEN.  Each ALEN is used as an index to a table to translate the ALEN
value into a STO.  A unique STO is thus obtained for each unique 2GB
region of the expanded virtual address space.

      A problem arises in expanded virtual addressing in that the
translation of the ALEN value to a STO is time consuming, and slows
down the cache data look-up operation.  Figures 1 and 2 describe a
control mechanism to avoid this loss in performance.

      In Figs. 1 and 2, an RX instruction is illustrated.  The B and
X fields point to AR/GR register pairs which together store 64 bit
virtual addresses.  These register contents and the D instruction
field are routed to the AGEN Adder, which computes a 64 b...