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Handling Multiple Type B Branches within the Same Cache Line

IP.com Disclosure Number: IPCOM000104066D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

Recording miss sequences in multiple levels associated with L1-Line addresses within the L2 CACHE directory must involve switching levels subsequent to a branch wrong guess on a TYPE B branch. The ability of handling multiple TYPE B branches within the same cache line as well as multiple entries to the same cache line is described.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Handling Multiple Type B Branches within the Same Cache Line

      Recording  miss sequences in multiple levels associated with
L1-Line addresses within the L2 CACHE directory must involve
switching levels subsequent to a branch  wrong  guess  on  a TYPE  B
branch.  The  ability  of  handling multiple TYPE B branches within
the same cache  line  as  well  as  multiple entries to the same
cache line is described.

      The organization of the L1-miss sequences within the context of
the  L2  Cache  directory  involves  associating all the successors
from a given L1-cache  line  with  that  L1-cache line  directory
entry  as  distinct  levels.  Each successor line-address was a
result of an actual miss generated by the L1-cache and such miss
addresses  are  recorded  so  as  to provide the full miss address.
In the case of an I-miss this includes the bits within the address
that specify the target instruction  HW  (Halfword) address.  This
allows prefetching that uses these addresses to be as well directed
as ordinary miss generated addresses are in their ability to deliver
the targeted line in the proper sequence.  A  given  L1-line  can
have   multiple   entries   as  distinguished  by  accessing
different HW's within the  line  and  associated  with  each entry
there  is  at  least one exit.   Multiple exits for a given entry
occur because of variable action/target, TYPE B, branches.

      The exit from a line must be associated with the line  entry so
that  in  the event of an alternative action of a TYPE B branch a new
exit can be linked to the old entry.  When HEDGE PREFETCHING is
attempted, the alternative exits from a given entry should also be
linked.  If there are two or more  TYPE B  branches within a line
that are encountered subsequent to a given entry there can be more
than  two  exits  associated with  a  given  entry  even if TYPE B
branches only have two alternative action/targets.

      UPDATING THE LEVEL INDICATOR OF THE PREDECESSOR FOLLOWING A BWG
- Within the predecessor of a given cache line, a level indicator
specifies the position of the corresponding exit-address as stored at
the location specified by the L1-line entry within the L2 dire...