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Si/SiGe Heterostructure MOS Devices with Step-Graded Bandgap Profile of the SiGe Channel

IP.com Disclosure Number: IPCOM000104084D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Zaslavsky, A: AUTHOR

Abstract

Disclosed is a performance-enhancing modification of the SiGe channel profile in Si/SiGe heterostructure MOS devices. Recently, there has been considerable interest in p-MOS Si/SiGe devices [1-4], where the carriers (holes) are confined in a narrow SiGe quantum well channel, rather than at the usual Si/gate oxide interface. These Si/SiGe devices exhibited higher carrier mobility and transconductance for two reasons: the Si/SiGe interface is an improvement over the standard Si/oxide interface and the carrier mobility in the channel is higher because the in-plane mass in the lowest-lying (first) quantum well subband is considerably smaller than in bulk Si.

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Si/SiGe Heterostructure MOS Devices with Step-Graded Bandgap Profile of the SiGe Channel

      Disclosed is a performance-enhancing modification of the SiGe
channel profile in Si/SiGe heterostructure MOS devices.  Recently,
there has been considerable interest in p-MOS Si/SiGe devices [1-4],
where the carriers (holes) are confined in a narrow SiGe quantum well
channel, rather than at the usual Si/gate oxide interface.  These
Si/SiGe devices exhibited higher carrier mobility and
transconductance for two reasons: the Si/SiGe interface is an
improvement over the standard Si/oxide interface and the carrier
mobility in the channel is higher because the in-plane mass in the
lowest-lying (first) quantum well subband is considerably smaller
than in bulk Si.  In such devices, optimal performance requires that
the carrier density in the first subband be maximized, but at the
same time the Fermi level should not approach the higher-lying
(second) subband, where the in-plane mass is higher and the mobility
is consequently degraded (see Fig. 1 for a schematic band diagram of
a standard device).  Evidently, increasing the energy separation (E
sub 2 - E sub 1) can contribute to better performance by increasing
the maximum achievable density in the first subband.  One possibility
is to increase the depth of the SiGe well by going to higher Ge
concentrations.  This has the disadvantage of reducing the critical
thickness of the well before dislocations set in [5]  and a narrower
well pushes E sub 1 up towards the Si band edge, reducing the maximum
carrier density in the well.  Proposed is an alternative technique,
the step-grading of the SiGe channel profile, that relies on the
difference in the subband wavefunctions to increase the subband
energy separation without increasing the Ge content.  In addition,
the step-graded channel profile reduces the lattice mismatch at the
Si/SiGe interfaces.  Finally, although all of the device work to date
has focused on p-MOS devices because the Si/SiGe band offset occurs
almost entirely in the valence band if unstrained Si substrates are
used, the same step-grading technicque can be applied to increase the
electron subband separation in n-MOS devices grown on relaxed SiGe
substrates.

      It follows from basic quantum mechanics that the wavefunction
&Psi.  sub n(x) of a carrier in the subband n of a potential well has
n nodes.  In particular, in a square potential well these
wavefunctions are approximately &Psi.  sub n(x) ~  n&pi.x/W,
where W is the well width (this result is exact for an infinitely
deep well).  Since the probability of finding the carrier at position
x is proportional to |&Psi.(x)| sup 2 it follows that the probability
amplitude of the carriers in the first subband is peaked at x = W/2
(center of the channel) and in the second subband at x ~
W/4, 3W/4 (see Fig. 2).  Consequently, the energy separation (E sub 2
- E sub 1) can be increased by symmetrically step-grading the
potenti...