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Processor Oriented Pipelining in Transaction Systems

IP.com Disclosure Number: IPCOM000104095D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

A better way to process transactions in a multiprocessor system is to pipeline the transaction processing using dedicated processors, that perform repetitively, specific functions. Tuning parameters on the mechanism that segments the overall process and dedicates processors to special segments can determine how many of the processors are specialized and how many retain their general purpose function. The process of specialization is incremental and each program segment that is specialized is determined by its own utilization within the overall multiprocessor configuration. This utilization determines how many processors should be specialized to this function, if any.

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Processor Oriented Pipelining in Transaction Systems

      A better way to process transactions in a multiprocessor system
is to pipeline the transaction processing using dedicated processors,
that perform repetitively, specific functions.  Tuning parameters on
the mechanism that segments the overall process and dedicates
processors to special segments can determine how many of the
processors are specialized and how many retain their general purpose
function.  The process of specialization is incremental and each
program segment that is specialized is determined by its own
utilization within the overall multiprocessor configuration.  This
utilization determines how many processors should be specialized to
this function, if any.  The release of a process, at the end of the
program-segment within specialized processor, can be considered a
normal task switch invocation and is done so that the special purpose
nature of the cache of this special purpose processor is not
perturbed.

      THE CONCEPT OF SPECIAL CASE HANDLING FOR PERFORMANCE
IMPROVEMENT - It is often the case that an improvement in processor
performance can be achieved by use of a special case handling of a
repetitive phenomena.  Within processor performance the persistence
of program behavior offers ample opportunity to identify repetitive
phenomena and it is only necessary to identify the peculiar advantage
that best suits the situation.  The performance advantage is derived
in comparison with the standard handling of the phenomena and usually
involves special hardware additions to:

o   Identify the occurrence of the phenomena, and
o   A means to achieve a performance improvement.

      A classic example of such a situation is the handling of cache
misses.  The cache miss penalty involves the delays associated with
accessing the immediate datum not present in the cache and other data
within the line.  Often the default sequence of transfer of the other
elements of a cache line is not optimum in minimizing the delay.  The
repetitive nature of the phenomena is assured by the persistence of
the patterns of access created by the code.  A means of resequencing
the elements of the cache line, so as to minimize processor delay,
benefits the performance associated with cache misses that are
created by such a code segment.  The overall approach in such matters
is to allow the processor to perform its basic function with
exception in specific situations.  In these situations, a
modification that has a performance advantage can be pursued.

      USING A MULTIPROCESSOR DESIGN AS A BASE CASE CONFIGURATION -
High End Processor (HEP) designs have always been uniprocessors and
multiprocessor configurations have been considered as an add-on.  To
support necessary requirements of the multiprocessor configuration
software and hardware extensions have been made only to the point
necessary to assure correct operation.  The role of the hardware
modifications, as the...