Browse Prior Art Database

Low Intra-Level Capacitance Wiring Structure

IP.com Disclosure Number: IPCOM000104098D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Ng, H: AUTHOR [+4]

Abstract

Disclosed is a process technology that produces a vertically offset wiring structure that significantly reduces line to line capacitance in ULSI memory, ULSI logic and Bipolar chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Low Intra-Level Capacitance Wiring Structure

      Disclosed is a process technology that produces a vertically
offset  wiring  structure  that significantly  reduces  line  to
line  capacitance  in ULSI memory, ULSI logic and Bipolar chips.

      The disclosed process is as follows:  CVD  deposit  the first
interlevel  passivation,  oxide  #1,  to  a thickness approximately
2000A  thicker   than   the   desired   metal thickness.  Deposit  a
layer  of  SiNx  approximately 1000A thick, which will act as a RIE
etch stop.  CVD  deposit  the second layer of oxide, oxide #2, the
same thickness as oxide #1.  Deposit  a  layer of AlOx 200-400A
thick, which will be used as a RIE etch mask.  The structure to this
point in  the process  is  shown in step A. Define the 1st M1 resist
line, which is referred to as  M1A,  using  standard  lithographic
techniques.  RIE  etch the AlOx and oxide #2 stopping on the SiN etch
stop layer, as shown  in  step  B.  Strip  the  M1A resist  etch
mask and photo pattern M1B as shown in step C.  RIE etch the SiNx
selectively to  the  AlOx  and  underlying device  isolation  as
shown  in  step E. Blanket Si implant using an approximate  dose  of
8E16/cm2  at  an  energy  of 25-30KeV.    Note  that a 'strike' layer
may be used to seed subsequent selective metal depositions.  If a
'strike'  layer is  used  then  the  Si implant can be eliminated.
Strip the AlOx using a...