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Multisequencing a Single Instruction Stream Use of the SFLA as a Means of Reducing Store-Fetch Interlock

IP.com Disclosure Number: IPCOM000104100D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+4]

Abstract

MSIS is a uniprocessor organization in which a set of processing elements (PEs) working in concert execute Segments of the instruction stream. The Segments are either P-Segments, normal uniprocessor instruction stream portions that are processed in the E-MODE of MSIS and produce Z-Segments, or the Z-Segments that are processed in Z-MODE by MSIS. The main difference between E-MODE and Z-MODE is that, during E-MODE, each PE sees all instructions in the Segment and executes the ones that are assigned to it, but during Z-MODE, a PE only sees the instructions assigned to it.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Multisequencing a Single Instruction Stream Use of the SFLA as a Means of Reducing Store-Fetch Interlock

      MSIS is a uniprocessor organization in which a set of
processing elements (PEs) working in concert execute Segments of the
instruction stream.  The Segments are either P-Segments, normal
uniprocessor instruction stream portions that are processed in the
E-MODE of MSIS and produce Z-Segments, or the Z-Segments that are
processed in Z-MODE by MSIS.  The main difference between E-MODE and
Z-MODE is that, during E-MODE, each PE sees all instructions in the
Segment and executes the ones that are assigned to it, but during
Z-MODE, a PE only sees the instructions assigned to it.

      As all PEs see all instructions in E-MODE, each PE can create
the Z-CODE it will require to re-execute the Segment as a Z-Segment,
the Z-CODE being stored in the Z-CACHE, and associated with
instructions in the Z-CODE are S-LISTS and D-LISTS as appropriate.
An S-LIST instructs the PE, in the Z-MODE, that one or more of the
source registers in an instruction assigned to it is set by another
instruction that is executed on another PE.  An S-LIST is a receiving
obligation.  The D-LIST instructs the PE in the Z-MODE as to the
names of PEs that require the values of the register(s) that are
being set by an instruction that is assigned to it.  A D-LIST entry
is a sending obligation.

      The SFLA ,STORE/FETCH LOOK-ASIDE, creates an alternate
execution path of the FETCH instructions in the presence of a valid
look-aside entry.  The SFLA is the set of STORE/FETCH bypass
registers, each having a BXD or an address mode of access, that can
be used as a search argument.  The handling of STORE/FETCH
interaction through a SFLA using BXD is quite different than the
pending store buffer on conventional processors.  For one, the
pending store buffer uses addresses rather than BXD.  In MSIS, the
pending store buffer is part of the OSC controls within the memory
hierarchy and the SFLA replicated in each PE and can monitor multiple
STORES executed by different PEs for validation within E-MODE and
operation within Z-MODE.

      Operand Store Compare, OSC, is a requirement of certain
architectures that a conceptually later fetch-instruction retrieves
the result of a conceptually earlier store-instruction.  A related
requirement in some architectures is Program Store Compare, PSC, that
requires that a Store Into the Instruction Stream must be detected so
that the updated instruction is the one actually executed.

      By scheduling STORE/FETCH pairs on the same PE, a reduction in
OSC will occur.  Further, the use of BXD, structural information
about instructions, allows the autonomous, asynchronous, scheduling
operation to be maintained while a significant state type phenomena
is avoided.  The implication of the use of look-asides does not
impact the MP aspects of MSIS if the FETCH is sent to the OSC
controls with the indicative information conc...