Browse Prior Art Database

Dual Processor User-Programmable Input/Output Processor

IP.com Disclosure Number: IPCOM000104110D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Remfert, JE: AUTHOR

Abstract

A method for providing a user-programmable I/O processor is disclosed. A user I/O program execution environment is provided in a manner that maintains overall system I/O bus integrity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dual Processor User-Programmable Input/Output Processor

      A method for providing a user-programmable I/O processor is
disclosed.  A user I/O program execution environment is provided in a
manner that maintains overall system I/O bus integrity.

      An overview of a typical computer system, including system
processor, I/O processors (IOPs), and system I/O bus is shown in Fig.
1.  IOPs that are user-programmable can co-reside on the system I/O
bus with IOPs that are not user-programmable.  The system I/O bus and
and associated resources are shared amongst the different types of
IOPs.

      Detailed hardware and program views of the user-programmable
IOP are shown in Fig. 2.  The focus of this disclosure is on the dual
processor architecture of the user-programmable IOP and the
capabilities provided by such an architecture.  A key element is the
relationship between the system processor and the dual processors of
the IOP, namely the system I/O processor and the user I/O processor.

      The system processor executes user application programs and
operating system programs.  The operating system programs include I/O
support programs which communicate with and control the IOPs on the
system I/O bus.  Control information and data is usually transferred
to the IOP via direct memory access (DMA), where the IOP functions as
a system I/O bus master.  (Some system I/O buses also use bus unit,
fixed length messages and associated interrupts to transfer control
information to/from IOPs.)

      The user-programmable IOP contains two processors: the system
I/O processor and the user I/O processor.  The system I/O processor
handles all system I/O bus communications with the system processor.
It can control the assigned system I/O bus DMA registers and process
associated system I/O bus interrupts.  The processor-to-processor
interface between the system I/O and user I/O processors can be
implemented via shared memory, local I/O bus, or processor bus logic.
The interface can contain hardware logic to assist the system I/O
processor with performing debug functions (e.g., start, stop, trace)
on...