Browse Prior Art Database

Early Floorplanning using Critical Block Transformation for (CPI*CT) Reduction

IP.com Disclosure Number: IPCOM000104112D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Bose, P: AUTHOR [+4]

Abstract

Disclosed is a process or methodology, wholly implemented in software, which can be used to design and implement hardware processor chips exhibiting higher overall performance (MIPS) than that achievable by current CAD design tools. The concept of (integrated) CPI*CT reduction disclosed in this article, involves the use of a workload (or program benchmark) in deriving or fine-tuning a CPU chip design (floorplan). The global cost function to be minimized, includes the product of cycles-per-instruction (CPI) and cycle-time (CT), thereby making this tool a novel, MIPS-driven physical design methodology. The attached figure illustrates the concept of workload-driven (CPI*CT) early floorplanning in functional flow-chart form.

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Early Floorplanning using Critical Block Transformation for (CPI*CT) Reduction

      Disclosed is a process or methodology, wholly implemented in
software, which can be used to design and implement hardware
processor chips exhibiting higher overall performance (MIPS) than
that  achievable  by  current  CAD  design  tools.  The concept of
(integrated) CPI*CT reduction disclosed  in  this article, involves
the  use  of  a  workload  (or  program benchmark) in deriving or
fine-tuning  a  CPU  chip  design (floorplan).    The  global  cost
function to be minimized, includes the product  of
cycles-per-instruction  (CPI)  and cycle-time   (CT),   thereby
making  this  tool  a  novel, MIPS-driven physical design
methodology.  The attached figure illustrates the concept of
workload-driven  (CPI*CT)  early floorplanning in functional
flow-chart form.

      The  major  difference  between this approach and prior work is
that the floorplanning process has the option and capability of
altering the area/time attributes of a given block, with the overall
goal of reducing the product of CPI and CT.  This is  accomplished
by  linking  the  main floorplanner to an early CPI estimator, which
predicts  CPI changes for block transformations.  A number of block
shape operators, e.g., DIVIDE, BISECT, DUP, etc. are  defined  for
use in  transforming  the  initial  netlist (graph) incrementally and
iteratively, during actual floorplanning.  Blocks  on  critical
(time)  paths,  which determine the CT performance of the  chip
floorplan,  are  identified  in  a critical  block/path   analysis
phase.  These  blocks  are candidates for area/delay adjustment to
reduce CT  at  the possible  cost  of  increasing  CPI.  Similarly,
blocks  in sub-critical paths may be increased  in  size  and/or
delay (without affecting overall CT) with the goal of reducing CPI
(and  hence  CPI*CT).  There are many possible variations of the
level of integration and  interaction  between  the  two estimation
phases  (CPI  related  and  CT  or  conventional floorplanning
related),  with  various  characteristics  and degrees of overall
performance enhancement.

      As  shown in the figure, the main inputs to the process are:
(a) an excitation trace  tape  or  workload; (b) an initial  netlist
of functional blocks, internally augmented with attributes linking
the blocks to the  higher-level CPU organization;  and (c)  an
organizational  parameter  file characterizing the CPU organization
(with implied  structure and  functional semantics), as used in  a
conventional cycle-by-cycle  timer  program.  The  elements (or
steps) comprising the present invention are listed below:

1.  Generating a set of tables to characterize the variation of
    cycles-per-instruction   (CPI)   performance,  with incremental
    (delta)   changes   in   processor    c...