Browse Prior Art Database

Parity Check Mechanism for B Adjacent Generated RS Double Correcting Code

IP.com Disclosure Number: IPCOM000104115D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR

Abstract

Disclosed is a mechanism that provides fast error checking of code generating or decoding circuits of an implementation of a Reed/Solomon double error correcting code. Mechanism predicts the resulting parity based on the input data and the binary bits in the Lambda Matrix. Circuits are checked by comparing the predicted parity with the generated parity.

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Parity Check Mechanism for B Adjacent Generated RS Double Correcting Code

      Disclosed is a mechanism that provides fast error checking of
code generating or decoding circuits of an implementation of a
Reed/Solomon double error correcting code.  Mechanism predicts the
resulting parity based on the input data and the binary bits in the
Lambda Matrix.  Circuits are checked by comparing the predicted
parity with the generated parity.

      Array DASD can be protected against double failures using RS
codes.  This disclosure teaches a mechanism that provides parity
protection for the circuits that code and decode the RS code
generated using a B Adjacent structure.  These codes are generated
using a square binary matrix called Lambda.  In this disclosure a
four by four matrix is used to code an eight bit plus parity byte, A,
into eight bits plus parity, B.  The four by four matrix is used to
code the byte in two four bit groups, a1 - a4 and a5 - a8.  The
matrix is loaded with 16 control bits c11, c12, ...  c44.  Figure 1
illustrates the matrix operation that transforms A into B. Figure 2
illustrates the binary algebra to derive the predicted parity of B
based on A, Lambda, and parity of A.  Figure 3 illustrates an
implementation of the parity prediction mechanism to check the
resulting output.  Note that the Lambda values are static during a
given transformation so the data rate of the checking circuits is
bound by the circuit delay of the "AND" gates and t...