Browse Prior Art Database

Burn-in/In Situ Testing of Computer Chips

IP.com Disclosure Number: IPCOM000104118D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Lueck, PJ: AUTHOR

Abstract

Described is an in-situ test for chips or substrates in which there is no permanent connection, and shearing forces exerted on the chip during its removal are eliminated.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Burn-in/In Situ Testing of Computer Chips

      Described is an in-situ test for chips or substrates in which
there is no permanent connection, and shearing forces exerted on the
chip during its removal are eliminated.

      Known production means are combined with a hydraulic bellows
and a special device such that the indispensible burn-in operation
involving solder joints may be carried out without a permanent
connection.  Existing burn-in methods use simulated carrier elements
to which the burn-in chip to be tested is soldered and from which it
has to be separated undamaged after burn-in.  These solutions are
problematic in a number of ways and require additional expensive
carrier means which have to be produced outside the standard
production process.  Substrates with LAP (limited area pads) are
produced, for example, with smaller C4 solder ball carrier surfaces
to reduce shearing forces during the chip's removal.  However, all of
these existing solutions are expensive, require solder steps and lead
to chips having to be scrapped during removal.

      According to the proposed concept, a carrier is produced in the
standard production line, and the pads are Au-coated instead of using
SnPb for the solder joint.  The very low junction resistance of gold
has many advantages.  Use of the same production line without
additional equipment saves money.  The carrier may be reused for the
same chip part number and is only subject to normal wear during
testing.

      The chips are inserted in a frame holder with chip nests to be
positioned relative to the carrier.  The two components, the
gold-plated chip substrate and the frame with the chips, are aligned
to each other by positioning pins or inserts and mounted in a holder
fitted with a hydraulic bellows acting as a permanent connection.

      The adjustable pressure joint replaces the solder joint and is
less expensive than solder and shearing steps.  This approach permits
the carrier to be used for a longer period of time an...