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Browse Prior Art Database

Managing a List of Output Control Blocks

IP.com Disclosure Number: IPCOM000104119D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Arnold, MA: AUTHOR [+3]

Abstract

APPC (Advanced Program to Program Communications) specifies that data be sent in packets equal in size to the maximum RU length defined for the session being used. Since the APPC transaction programs are unaware of RU length and send data in arbitrary size packets, a mechanism is needed to convert the transaction program packets into APPC RUs. The present mechanism is to copy the data into a buffer equal in size to the maximum RU size allowed for the session being used, and when this buffer is filled (or when an event occurs on the API which requires transmission [hereafter known as a "FLUSH event"]), it is sent through the SNA layers of code and it is further copied into a link buffer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Managing a List of Output Control Blocks

      APPC (Advanced Program to Program Communications) specifies
that data be sent in packets equal in size to the maximum RU length
defined for the session being used.  Since the APPC transaction
programs are unaware of RU length and send data in arbitrary size
packets, a mechanism is needed to convert the transaction program
packets into APPC RUs.  The present mechanism is to copy the data
into a buffer equal in size to the maximum RU size allowed for the
session being used, and when this buffer is filled (or when an event
occurs on the API which requires transmission [hereafter known as a
"FLUSH event"]), it is sent through the SNA layers of code and it is
further copied into a link buffer.

      The above mechanism causes at least one needless copy of the
transaction programs data.  As copying of data from one buffer into
another is expensive in both processor cycles and processor MIP rate
(it has been shown that in certain processors with an instruction
cache, the movement of data can affect the contents of the cache and
significantly slow down the processor until the cache becomes
rebuilt), we have invented a mechanism which (depending on the DLC
implementation) can either eliminate all data moves or reduce them to
a single move from the transaction programs buffer into the DLC link
buffer.

      A key purpose of this invention is to allow less data movement
than previous designs.  Previous designs required that data first be
moved from the user's buffer into an intermediate buffer, and then
later moved into an I/O buffer.  This design eliminates the first of
those moves by allowing the data to be moved directly from the users
buffer to an I/O buffer.

      A further saving can be achieved by having a channel which can
do gather writes, thus eliminating the other data movement (data
could be written directly from the users buffer to the channel).

However, this capability would eliminate one of the moves in both the
previous design and the invention design, and is not a part of this
disclosure.

      The invention specifies that the half-session maintains a list
of control blocks waiting to be sent to path control.  A control
block is added to this list when the transaction program (TP) sends
one to the half-session.  After adding the control block to the list,
the half- session checks to see if the TP requested that the control
block be sent on the line (this is known as a FLUSH event).  If the
TP did not specify a FLUSH event, the half-session will check to see
if the following conditions are met:

1.  Does the total length of the data in the control block list
    exceed the maximum RU length allowed for this session?

2.  Is the pacing list empty (i.e., are any control blocks waiting
    for a pacing response)?

3.  Is the residual pacing count > 0?

If all of these are true, the half-session checks to see if another
contr...