Browse Prior Art Database

VLSI Chip Scan-Ring Read and Modify via Fiber Optic Serial Link

IP.com Disclosure Number: IPCOM000104120D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Chung, VE: AUTHOR [+2]

Abstract

An internal chip process that can service the chip scan ring through the fiber optic serial link interface is disclosed. This can be applicable to any fiber optic link or any other communications medium.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

VLSI Chip Scan-Ring Read and Modify via Fiber Optic Serial Link

      An internal chip process that can service the chip scan ring
through the fiber optic serial link interface is disclosed.  This can
be applicable to any fiber optic link or any other communications
medium.

      This process allows reading and modifying a VLSI chip scan ring
without a service processor to toggle the A and B clocks or
monitoring the SDO.  The chip does this internally.

      The chip sends a complete copy of its scan ring in a serial
link frame and the chip can update its scan ring based on a serial
link frame input.  All this is done internally by the chip.

      Through the use of an external pin, the chip can send a serial
link frame containing a copy of its scan ring.

To accomplish this, the chip was structured to have the following:

1.  Two groups of logic domain in separate clock trees, one to handle
    functional logic called functional logic and the other to handle
    scan ring servicing called service logic.

2.  Special clock tree control to turn off and control functional
    logic A and B clocks while keeping the service logic clocks on.

3.  The chip should contain an array with a number of bytes
    sufficient to contain the entire scan ring.  This array is used
    during functional mode to buffer fiber data transmissions.  This

    array was placed in the service logic domain to allow its use in
    scan service.

      Functional logic performs the normal chip function.  One of its
main functions is to handle the serial link interface.  A token frame
is received by the functional logic which sets a flag, entering scan
service mode.

      During scan service mode, the service logic uses the clock tree
control logic to turn off the functional clocks and to toggle the A
and B clocks of the functional logic.  Once the scan service is
completed, the functional clocks are turned back on.

The service domain consists of two parts:

1.  The scan controller is present on the chip for other reasons and
    is extended for this invention.  The scan controller can be
    proprietary or conform to a standard such as IEEE 1149.1.  Most
    needed scan functions are already in the scan controller.  The
    original purposes of the scan controller are:

    o   Direct connect to service processor
    o   Built-in chip test

2.  The array and its controls, or the communications link interface
    logic, are separated from the functional logic in clock control
    only.

    The array or communications link logic can be tested by the scan
    controller even though it is in the service domain for the
    purposes of this invention.

          Care was exercised to gate functional logic control that
    manipulates the array during scan service mode.  The following
    sections explain how the scan ring read and modify process work.

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