Browse Prior Art Database

L2-Inversion-Control of the Multiprocessor Misses from the L2

IP.com Disclosure Number: IPCOM000104126D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

Operation of a multiprocessor configuration can be enhanced by specializing processors to the functions that they are primed to perform. This specialization can be enhanced by transferring data to these processors on a timely basis using an existing prefetching mechanism. What has occurred in this system is that cache misses to an increasing degree have become subject to the control of the L2.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

L2-Inversion-Control of the Multiprocessor Misses from the L2

      Operation of a multiprocessor configuration can be enhanced by
specializing processors to the functions that they are primed to
perform.  This specialization can be enhanced by transferring data to
these processors on a timely basis using an existing prefetching
mechanism.  What has occurred in this system is that cache misses to
an increasing degree have become subject to the control of the L2.

In existing systems cache misses occurred under the principle of
maximum surprise.  When a processor missed in its cache the memory
hierarchy was prepared in some standard way to provide for access to
the missed datum.  The degree to which misses can be anticipated in
the types of  multiprocessing systems described by PROCESSOR
PIPELINING allows more control and anticipation by the L2 for both
I-CACHE and D-CACHE misses.

      Advantages in performance can be achieved within a
multiprocessing system by specializing, on a dynamic basis,
processors to specific program segments.  The schematic of the
processing of a homogeneous workload can be altered so that, as shown
below, the view of going between stages of processing is altered into
the view of going between individual processors.

PROCESSOR PIPELINING IN TRANSACTION SYSTEMS

*----------*----------*----------*----------*
|    S1    |    S2    |    S3    |   S4     |
*----------*----------*----------*----------*

*----------*----------*----------*----------*
|    P1    |    P2    |    P3    |   P4     |
*----------*----------*----------*----------*
where P1, P2, ...  are processors that execute S1, S2, ...

      The program segments are determined based on tuning parameters
and other aspects of the workload.  Each Program Segment that has a
processor specialized is initiated by a PT (Processor Transition) and
terminated by a PT.  The machine state at the beginning of each such
stage of processing is transferred insofar as register contents.  The
I-Cache contents  are  the result of the prior execution of the same
function and therefor presumed appropriate.  It is the D-Cache
contents that concerns us in this disclosure.

      There are two basic approaches to handling the issues
concerning D-CACHE contents for the transferred-to-processor, TOP, as
relate to the D-CACHE contents of the tr...