Browse Prior Art Database

Hardware Instruction Generation

IP.com Disclosure Number: IPCOM000104133D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 163K

Publishing Venue

IBM

Related People

Handlogten, GH: AUTHOR

Abstract

Some floating point operands (sources and/or results) require special handling, making hardware execution difficult. Denormalized sources may require prenormalization before they can be given to a particular execution unit. Some intermediate results must have their formats altered for completion of an operation. For example, enabled overflows and underflows must have their exponents altered while disabled underflows require denormalization.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Hardware Instruction Generation

      Some floating point operands (sources and/or results) require
special handling, making hardware execution difficult.  Denormalized
sources may require prenormalization before they can be given to a
particular execution unit.  Some intermediate results must have their
formats altered for completion of an operation.  For example, enabled
overflows and underflows must have their exponents altered while
disabled underflows require denormalization.

      This invention provides an efficient manner to perform many
types of difficult operations in hardware.  The control logic
performs the difficult operations by breaking the function into basic
instructions the hardware can already easily perform.  Special
hardware is kept to a minimum by making the iterations behave like a
series of simple instructions.  Most of the logic is unaware of the
"big picture" and sees only a request for normal operation.  This
causes existing data paths to be automatically selected by the
existing control logic instead of being handled by special case
hardware.

      When an instruction requiring special handling is detected, a
copy of the instruction is placed into a backup register.
Instructions generated by hardware are inserted into the instruction
stream.  These "synthetic" instructions are in the same format as the
regular instruction set of the machine.  The hardware can produce the
instructions required to obtain the desired result.  The source and
destination fields for the synthetic instructions must be carefully
selected.  While synthetic results may be used by subsequent
instructions, their results are not written to the actual destination
specified by the instruction and they do not produce exceptions.

      If an algorithm can be structured so that results are used as
soon as they are produced, they can be bypassed directly from the
result stage back into the pipeline.  By causing data dependencies
between selected synthetic instructions, the results are used as
sources of subsequent instructions.  The last iteration will write
the final result to the original destination obtained from the backup
register.

      Some hardware units require that denormalized floating point
numbers first be prenormalized (fraction shifted and exponent
adjusted).  Prenormalization may be accomplished by the following
method.  Upon detection of a denormalized number used by instruction
N, a copy of N is placed in the backup register.  An ADD instruction
(with one operand forced to zero) is generated by the hardware for
each denormalized source operand.  Although not required for the
invention, the remainder of the discussion will assume imprecise
exceptions with either register renaming or appropriate address
checking, thereby allowing instructions to execute out of order.  The
synthetic ADD(s) are inserted into the instruction stream after
instruction N+1 has had a chance to enter the pipeline (N+...