Browse Prior Art Database

Shared L1 Cache

IP.com Disclosure Number: IPCOM000104135D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 6 page(s) / 185K

Publishing Venue

IBM

Related People

Brenza, JG: AUTHOR

Abstract

This invention describes a multi-processor (MP) computer system in which a special control mechanism and companion set of protocols are provided to enable two or more processors (CPUs) to share a common L1 cache with high efficiency. In today's systems, L1 caches are generally not shared. They are usually packaged as near as possible to the single CPU they service for best performance. With improved, denser circuit and array chip technologies, it becomes possible to package two or more processors on a single substrate (module or board). In this environment, it becomes highly desirable to share a common L1 cache, also packaged on the same substrate, which is equally near to both (or more) CPUs. Advantages include reducing cables and pins at the next higher level system component (SCE of Fig.

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Shared L1 Cache

      This invention describes a multi-processor (MP) computer system
in which a special control mechanism and companion set of protocols
are provided to enable two or more processors (CPUs) to share a
common L1 cache with high efficiency.  In today's systems, L1 caches
are generally not shared.  They are usually packaged as near as
possible to the single CPU they service for best performance.  With
improved, denser circuit and array chip technologies, it becomes
possible to package two or more processors on a single substrate
(module or board).  In this environment, it becomes highly desirable
to share a common L1 cache, also packaged on the same substrate,
which is equally near to both (or more) CPUs.  Advantages include
reducing cables and pins at the next higher level system component
(SCE of Fig. 1), since the shared L1 subsystem has a common set of
cables and controls to service L1/L2 cache transactions for both
CPUs.  Also, if both (or more) CPUs share a 2X capacity L1 cache
rather than each CPU having a private 1X capacity L1 cache, the
instructions per cache miss ratio is substantially improved for both
CPUs for the same cache hardware cost.  Also, with the protocols as
specified in this description, there is practically zero MP
degradation within the shared L1 subsystem of Fig. 1.  Similarly, for
MP configurations containing multiple shared L1 subsystems, the
overall MP system degradation is greatly reduced.

      The following description is, in part, an enhancement to a
processor system such as that of [*], which describes a Partitioned
Cache with PLAT Control Array.  More generally, this control
mechanism with companion protocols applies to any L1 cache structure
with a multi-port feature, sharable by multiple CPUs.  In these
cases, small sub-directories (SD's) would be used in place of the
PLAT's of [*]  to store the addresses of recently reference L1 lines
and to store the shared cache protocol control data.  The general
case using SDs is described herein.

      A general MP system diagram composed of one or more shared L1
cache subsystems is illustrated in Fig. 1.  The control mechanism for
implementation of the shared L1 cache protocols is illustrated in
Fig.  2.  The protocol rules for the shared L1 cache are tabulated in
Table 1.

      In Fig. 1, an MP system may be composed of multiple main
memories (L3), multiple SCEs with L2 cache, and shared L1 subsystems
with multiple CPUs attached.  The shared L1 is a multi-ported cache
to enable parallel, independent access paths by the multiple CPUs.
The shared L1 cache subsystem contains the data transfer and control
linkages to the SCEs, the L1 cache arrays, directory arrays, and
control arrays.  Each CPU contains instruction processing logic,
execution processing logic, and fetch/store linkages to the shared L1
cache.  Four control arrays are identified in Fig. 1 as follows:

o   SD-L #1:Sub-Directory (or PLAT)-Local, assigne...