Browse Prior Art Database

Multprocessor for Multiprotocol Router Systems

IP.com Disclosure Number: IPCOM000104154D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Serpanos, DN: AUTHOR [+2]

Abstract

Disclosed is a multiprocessor architecture for multiprotocol routing which achieves high performance by using dedicated, optimized processors to different protocols. A router employing this architecture can support a large number of protocol stacks with a modest number of processors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Multprocessor for Multiprotocol Router Systems

      Disclosed is a multiprocessor architecture for multiprotocol
routing which achieves high performance by using dedicated, optimized
processors to different protocols.  A router employing this
architecture can support a large number of protocol stacks with a
modest number of processors.

      Conventional multiprotocol routers do not meet the requirements
of high speed networks because of the low processing power they
employ.  Available multiprotocol routers do not achieve throughput
higher than a few tens of Mbps per link.  Resolution of the protocol
processing bottleneck is necessary to meet the requirements of
conventional and emerging high speed networks such as FDDI [1], ATM
at OC-3 and OC-12 rate, and  FFOL [2].

      Conventional routers are typically organized as a collection of
network adapters interconnected through a high speed bus, which can
be upgraded to a faster interconnection (e.g., multiple busses,
multistage network, or crossbar) as performance requirements
increase.  Typical adapters employ uniprocessor or specialized
architectures for protocol processing.  Therefore, incoming packets
to an adapter are stored and then processed by a single processor,
which identifies the protocols that need to be executed and, after
their execution, it forwards the packets to the appropriate adapter
for transmission.  Uniprocessor adapter architectures cannot achieve
high performance for high speed networks.  In case of FDDI, for
example, offering 100 Mbps, the processor can achieve media speed for
packets longer than 250 Bytes, when a total 300 instructions of
protocol processing are executed on a processor offering effectively
15 MIPS.  This estimation is optimistic, since context switching is
disregarded, and the processing overhead is optimistic considering
that FDDI packets require both LLC and routing protocol processing in
a router.

      Resolution of the processing bottleneck and support of high
speed networks can be achieved by employing a multiprocessor
architecture such as the one disclosed in this invention.  The
functional organization of the disclosed architecture is shown in
Fig. 1.  Dedicated Processing Modules (PMs) execute the various
protocols (LLC, IP, Decnet IP, etc.).  The first level of PMs,
denoted as Link Modules, is responsible for executing the physical
and Data Link Control protocols associated with the networks attached
to them.  In an FDDI attachment, for example, the corresponding PM
includes the physical layer protocol, the MAC and the IEEE 802.2
protocol as specified in the FDDI standard.  Since multiple routing
protocols may be using the same interconnection link, a routine,
PMUX, performing protocol (de)multiplexing on a single link, receives
packets from the DLC and forwards them to the appropriate routing
protocol module.

      After PMUX identifies the routing protocol (and thus the
associated PM), it forwards th...