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Browse Prior Art Database

Low Power Oriented Cell Placement

IP.com Disclosure Number: IPCOM000104155D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Miyoshi, A: AUTHOR [+2]

Abstract

Disclosed is a placement and wiring technology for CMOS gate array chip to decrease power consumption.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Low Power Oriented Cell Placement

      Disclosed is a placement and wiring technology for CMOS gate
array chip to decrease power consumption.

      There are two factors that determine the amount of power
dissipated in a CMOS gate array chip.  These are:

1.  Charging and discharging of output capacitive load
2.  Transient current in CMOS transistors

To decrease the power consumption of a chip, it is important to
minimize these two factors.  The output capacitive load mainly has
two factors.  One is wiring nets and the other is gate capacitance.
In gate array, W/L is determined by the size of basic cells.  So it
is impossible to reduce gate capacitance.  But the capacitance of
wiring net can be minimized by reducing wiring net length.  The power
dissipation of a signal line is given by the following expression:

1 over 2 CFV sup 2
where, C = capacitance
          F = frequency
          V = voltage

      The fastest input signal (normally, clock signal) is usually
divided by 2 as the signal propagates through a logic stage.  So the
power consumption of the fastest input signal net is twice or more
than other nets.  Therefore, reducing the net length of the fastest
input signal line is important to decrease the power consumption of a
chip.  The fastest input signal (clock signal) is mainly applied to
the clock input of flip-flops.  For these reasons, it is desirable to
put together flip-flops in a specific region of a chip.  By gathering
all flip flops in a specific area, clock signal lines can be
shortened and about 10 % of power consumption can be saved.

      By specifying the flip-flop region, it is also possible to
design the W/L factor of flip-flops to further reduce power
consumption since the region is occupied by flip-flops and does not
include combination logic .  The power dissipation of a flip-flop is
three times more than that of a 2-way NAND.  The power dissipation
can be decreased to half, without increasing propagation delay, by
reducing the W/L factor of internal gate of a flip-flop to half that
of output buffer of the flip-flop.

      Based on the above consideration, following is an effective way
to reduce power consumption of a chip:

1.  Put all flip-flops together in a specific r...