Browse Prior Art Database

Providing the Location of the Base Address that Causes a D-Miss

IP.com Disclosure Number: IPCOM000104190D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

A superior prefetching strategy for D-CACHE lines is to use I sub VALUE x D sub VALUE -> D sub LOC as opposed to I sub LOC x D sub LOC -> D sub LOC.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Providing the Location of the Base Address that Causes a D-Miss

      A superior prefetching strategy for D-CACHE lines is to use
I sub VALUE x D sub VALUE -> D sub LOC
as opposed to
I sub LOC x D sub LOC -> D sub LOC.

A means of providing this information at the time of a cache miss is
disclosed.

IMPROVEMENTS IN I X D -> D PREFETCHING - The manner of improvement in
the D prefetching is to incorporate the value changes in the prefetch
mechanism.  We realize that I x D -> D is a way of expressing
I sub LOC x D sub LOC -> D sub LOC
which is intended to be a surrogate for
I sub VALUE x D sub VALUE -> D sub LOC
as these represent:

o      I sub VALUE - the instruction which makes the access,
o      D sub VALUE - the value of the GPR, and
o      D sub LOC - the line that will be accessed,
respectively.  Now instructions do not change but data can easily be
modified.  The corrected form of the prefetching is
I sub LOC x D sub VALUE -> D sub LOC
and the prefetching mechanism is organized around the I-LINE, and for
each I-LINE, has a table of D sub LOC that are monitored for their
values.  For each D sub VALUE within the I sub LOC a target D sub
LOC, the line that will be accessed next, is specified as a prefetch
target.

      The information within the I sub LOC x D sub VALUE -> D sub LOC
prefetch mechanism is garnered from the historical use of the code.
Each processor on its cache misses presents to such a mechanism the
information that would have allowed prefetching: the location and
value of the register that generated the access that caused the miss.

PROCESSOR DESIGN MODIFICATION - Let us consider the GPR LOCATION
TABLE (GLT) which for each of the 15 GPR that can be used for Address
Generation (AGEN) contains, if valid, the address from which the
current contents of the GPR was LOADED.  Entries within this GLT are
invalidated by any instruction that modifies the value of the GPR
associated the entry.  The entry in the GLT is made at the time of
the AGEN operation of the LOAD instruction which places the value
from memory at the location specified by entry into the...