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Bit-by-Bit Maximum-Likelihood Detection of '1-D' Partial Response

IP.com Disclosure Number: IPCOM000104193D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Wood, RW: AUTHOR

Abstract

Existing methods of maximum likelihood detection of partial response all require feedback from immediately preceding decisions. This feedback loop limits the maximum rate at which such detectors can operate. Here, a bit-by-bit detector is p roposed which has no feedback and can be pipelined to operate at very high data rates. The approach takes advantage of the maximum run-length constraint, d, normally built into a code and can be pipelined to operate at very high data rates. The appr oach may also be applied to recognize the alternation of peaks on a digital peak-detect channel and, thus, provide a stronger gating function.

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Bit-by-Bit Maximum-Likelihood Detection of '1-D' Partial Response

      Existing methods of maximum likelihood detection of partial
response all require feedback from immediately preceding decisions.
This feedback loop limits the maximum rate at which such detectors
can operate.  Here, a bit-by-bit detector is p roposed which has no
feedback and can be pipelined to operate at very high data rates.
The approach takes advantage of the maximum run-length constraint, d,
normally built into a code and can be pipelined to operate at very
high data rates.  The appr oach may also be applied to recognize the
alternation of peaks on a digital peak-detect channel and, thus,
provide a stronger gating function.

      The implementation for '1-D' is based on the following
algorithm: A sample (y(kT), represents a transition from NRZ zero to
NRZ one if it exceeds two qualifying samples, y((k-L)T) and
y((k+M)T), by an amount H and also exceeds all intervening samples or
if it is below two qualifying samples, y((k-L)T) and y((k+M)T), by an
a mount H and is also below all intervening samples.  [L and M are
integers less than or equal to d+1; H is a threshold nominally equal
to 2 for samples with va lues -2,0,+2.].

      The figure shows an implementation of this algorithm for a
simple d,k=0,2 with six-bit input samples.  The current sample is
compared with the six adjacent samples using only three comparators
and a number of delay registers.  In addition, five-bit rather th...