Browse Prior Art Database

Hybrid Automatic Gain Control

IP.com Disclosure Number: IPCOM000104203D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18

Publishing Venue

IBM

Related People

Garcia, R: AUTHOR

Abstract

The hybrid AGC behaves similar to its analog AGC equivalent. In the digital realm, the analog signal is sampled and processed digitally. This model uses the envelope of the incoming signal to determine its peak value during the AGC sampling period. This particular design is sensitive to noise in the signal, just as its analog equivalent is sensitive to noise.

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Hybrid Automatic Gain Control

      The hybrid AGC behaves similar to its analog AGC equivalent.
In the digital realm, the analog signal is sampled and processed
digitally.  This model uses the envelope of the incoming signal to
determine its peak value during the AGC sampling period.  This
particular design is sensitive to noise in the signal, just as its
analog equivalent is sensitive to noise.

      Fig. 1 shows the high level representation of the hybrid AGC.
The incoming analog signal must pass through an anti-aliasing filter
for the AGC to work properly.  The AGC uses the filtered data from
the digital filter.  The AGC algorihm is shown in Fig. 2.

      The variable gain amplifier band limits the incoming signal,
which provides anti-aliasing for the digital filter.  The digital AGC
samples the data flowing out of the digital filter, calculates the
new gain correction and closes the loop by adjusting the gain on the
amplifier.

      The digital AGC algorihm is shown in Fig. 2.  x(nT) represents
the data stream.  x(n) and max[x(n)]  use the data sampling clocks to
load data.  max[x(n)]  uses the data sampling clocks divided by some
constant to generate an AGC sampling clock that samples at least one
period of the lowest frequency component of the incoming signal.  The
accumulator is updated on the trailing edge of the AGC sampling clock
to avoid race conditions and erroneous calculations.

      The digitized data can be in signed magnitude form or signed
two's complement form.  At initial power-up, all registers and the
accumulator are set to zero.  As the data flows into the digital AGC,
the incoming data is latched into the register x(n).  The incoming
data is compared to the data in register max[x(n)].  Whenever the
data in x(n) is greater than max[x(n)], the data in x(n) is shifted
into max[x(n)].  Whenever x(n) <=  max[x(n)], the value of max[x(n)]
remains unchanged.

      The look up table and algorithm are discussed in detail in
following sections.

      The gain control signal to the amplifier is controlled by the
output of the accumulator.  Rather than work with absolute values,
the accumulator works with relative values.  For example, if the
previous value from the accumulator did not provide the correct gain
for the incoming signal, the look-up table will generate a new
correction factor (&Delta.p) to either increment or decrement the
accumulator from its current value.  By using relative values, the
accumulator can compensate for variations between the analog
amplifiers response to the gain control voltage.

      The algorithm is simulated using the C-program model in the
SOFTWARE MODEL section.  Fig. 3 shows and input signal that has a
sudden change in signal level (such as those experienced during
signal drop outs).  The hardware starts with no signal coming in,
then a signal at one level and then shifted to another level.  Fig. 5
shows the gain corrections for t...