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Using an Entry-Exit Map for L2-Based Cache Line Prefetching

IP.com Disclosure Number: IPCOM000104220D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

The set of L1-line exits, maintained by a L2-directory for L1 cache line prefetching, provides a means to coordinate multiple processors being prefetched for based on local status of their own BHT (Branch History Tables). That which distinguishes prefetching based on the set of exits from a line as maintained as separate levels within the L2 directory relates to:

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This is the abbreviated version, containing approximately 52% of the total text.

Using an Entry-Exit Map for L2-Based Cache Line Prefetching

      The set of L1-line exits, maintained by a L2-directory for L1
cache line prefetching, provides a means to coordinate multiple
processors being prefetched for based on local status of their own
BHT (Branch History Tables).  That which distinguishes prefetching
based on the set of exits from a line as maintained as separate
levels within the L2 directory relates to:

o   the commonality of exits across processors attached to the L2
    that can support a form of HEDGE PREFETCHING.
o   The time of retention of this information as distinguished from
    time of retention in a BHT.
o   The removal of the prefetching function from a speed critical
    region of the processor design.

The manner of prefetching for L1 caches that are attached to an L2
cache can operate in conjunction with the set of line exits
incorporated as levels maintained for each L1-cache line by the L2
cache directory.  The information kept within the L2 cache directory
for each L1 cache line can be visualized as a switching center that
links entries to the line with their exits from the line.  Thus, a
predecessor of a line has the line entry point of its successor as
one of its exit levels and a level index that specifies which exit
from that successor line is to be used.

Two issues complicate this approach:

1.  In an MP environment the status of the Branch History Tables,
    BHTs, within the separate processors may be different.  The
    separate processors may be at different points in their execution
    sequences of common code.  The prefetching needs to be relevant
    to individual processors.

2.  The alteration of a Branch action, the action/target change of
    TYPE B branch, can affect the exit for multiple entries into a
    line including the entry which reused the branch.

      A model for the process of switching needs to recognize that
the exits from the lines are usually well established but the action
alteration of branches af...